• Title/Summary/Keyword: Programmable Filter

Search Result 95, Processing Time 0.029 seconds

A Programmable High-Pass Filter Based Stator Flux Estimation for a Direct Vector Controlled Induction Motor Drive System (프로그램어블 고역필터를 사용한 직접 벡터제어 유도전동기 구동시스템의 고정자 자속 계산)

  • Jeon, Tae-Won;Choe, Myeong-Gyu
    • The Transactions of the Korean Institute of Electrical Engineers B
    • /
    • v.49 no.1
    • /
    • pp.48-53
    • /
    • 2000
  • The novel integration method with programmable high-pass filter is suggested in order to solve the problem of integration for stator flux estimation in a stator flux oriented direct vector controlled induction motor drive system. The dc offset in a pure integrator is eliminated using high-pass filter with fixed time constant, and then time constant of programmable high-pass filter is controlled with a inverter frequency for integration in a wide frequency range, considering phase lag and attenuation due to both the hardware low-pass filter and high-pass filter. The proposed method is verified with the experimental results implemented by 32-bit DSP.

  • PDF

An Efficient Design of Programmable Down Converter for Software Radio (소프트웨어 라디오 수신기의 구현을 위한 효율적인 Programmable Down Converter 설계)

  • Gwak, Seung-Hyeon;Kim, Jae-Seok
    • Journal of the Institute of Electronics Engineers of Korea SP
    • /
    • v.39 no.1
    • /
    • pp.87-96
    • /
    • 2002
  • This paper proposes an efficient decimation filter structure in programmable down converter for software radio. The decimation filter consists of the cascaded integrator-comb(CIC) filter, a compensation filter for CIC, cascaded comb and modified halfband filters, and programmable FIR filter. Since the compensation filter is used in CIC, the passband drooping is compensated and stopband attenuation is improved. Therefor the more decimation can be implemented in CIC filter. The compensation filter in CIC reduced the computational complexity of other decimation filters and the coefficients of PFIR, thereby achieving a significant hardware reduction over existing approaches. We can reduce the multiply operator by 20% in hardware and operation by 50% as compared with PDC of Harris.

A Modified SaA Architecture for the Implementation of a Multiplierless Programmable FIR Filter for Medical Ultrasound Signal Processing (곱셈기가 제거된 의료 초음파 신호처리용 프로그래머블 FIR 필터 구현을 위한 수정된 SaA 구조)

  • Han, Ho-San;Song, Jae-Hee;Kim, Hak-Hyun;Goh, Bang-Young;Song, Tai-Kyong
    • Journal of Biomedical Engineering Research
    • /
    • v.28 no.3
    • /
    • pp.423-428
    • /
    • 2007
  • Programmable FIR filters are used in various signal processing tasks in medical ultrasound imaging, which are one of the major factors increasing hardware complexity. A widely used method to reduce the hardware complexity of a programmable FIR filter is to encode the filter coefficients in the canonic signed digit (CSD) format to minimize the number of nonzero digits (NZD) so that the multipliers for each filter coefficients can be replaced with fixed shifters and programmable multiplexers (PM). In this paper, a new structure for programmable FIR filters with a improved frequency response and a reduced hardware complexity compared to the conventional shift-and-add architecture using PM is proposed for implementing a very small portable ultrasound scanner. The CSD codes are optimized such that there exists at least one common nonzero digit between neighboring coefficients. Such common digits are then implemented with the same shifters. For comparison, synthesisable VHDL models for programmable FIR filters are developed based on the proposed and the conventional architectures. When these filters have the same hardware complexity, pass-band ana stop-band ripples of the proposed filter are lower than those of the conventional filter by about $0.01{\sim}0.19dB$ and by about $5{\sim}10dB$, respectively. For the same filter performance, the hardware complexity of the proposed architecture is reduced by more than 20% compare to the conventional SaA architecture.

소프트웨어 라디오 시스템을 위한 계산이 간단한 디지털 채널라이저의 설계

  • 오혁준;심우현;이용훈
    • The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.10 no.3
    • /
    • pp.2-17
    • /
    • 1999
  • Interpolated second order polynomials(ISOP's) are proposed to design efficient cascaded integrator-comb(CIC)-based decimation filters for a programmable downconverter. It is shown that some simple ISOP's can effectively reduce the passband droop caused by CIC filtering with little degradation in aliasing attenuation. In addition, ISOP's are shown to be useful for simplifying halfband filters that usually follow CIC filtering. As a result, a modified half band filter(MHBF) is introduced which is simpler than conventional halfband filters. The proposed decimation filter for a programmable downconverter is a cascade of a CIC filter, an ISOP, MHBF's and a programmable finite impulse response(FIR) filter. A procedure for designing the decimation filter is developed. In particular, an optimization technique that simultaneously designs the decimation filter is developed. In particular, an optimization technique that simultaneously designs the ISOP and programmable FIR filters is presented. Design examples demonstrate that the proposed method leads to more efficient programmable downconverters than existing ones.

  • PDF

A Fully Differential RC Calibrator for Accurate Cut-off Frequency of a Programmable Channel Selection Filter

  • Nam, Ilku;Choi, Chihoon;Lee, Ockgoo;Moon, Hyunwon
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.16 no.5
    • /
    • pp.682-686
    • /
    • 2016
  • A fully differential RC calibrator for accurate cut-off frequency of a programmable channel selection filter is proposed. The proposed RC calibrator consists of an RC timer, clock generator, synchronous counter, digital comparator, and control block. To verify the proposed RC calibrator, a six-order Chebyshev programmable low-pass filter with adjustable 3 dB cut-off frequency, which is controlled by the proposed RC calibrator, was implemented in a $0.18-{\mu}m$ CMOS technology. The channel selection filter with the proposed RC calibrator draws 1.8 mA from a 1.8 V supply voltage and the measured 3 dB cut-off frequencies of the channel selection LPF is controlled accurately by the RC calibrator.

A Design of Programmable Low Pass Filter to Reduce the ZCP Estimation Error at High Speed BLDC Sensorless Drive (BLDC 고속 센서리스 구동의 ZCP 추정 오차 저감을 위한 Programmable Low Pass Filter 설계)

  • Seo, Eunjeong;Lee, Kangseok;Lee, Wootaik
    • The Transactions of The Korean Institute of Electrical Engineers
    • /
    • v.63 no.1
    • /
    • pp.35-41
    • /
    • 2014
  • This paper presents a design method of programmable low pass filter(PLPF) which reduce an estimation error of a zero crossing point(ZCP) for a high speed brushless DC(BLDC) motor drive. BLDC motor sensorless drive is possible by estimation of ZCP. The ZCP estimated by detecting a change of back-EMF polarity has the estimation error because noises exist on the measured back-EMF. Therefore a calculated commutation timing using the ZCP is inaccurate. And the inexact commutation timing leads to ripples of 3-phase current and degradation of drive performance. This paper proposes the design method of the PLPF to overcome these problems. First, a speed calculated a inaccurate period of the ZCP is analyzed in the frequency domain. Then, the PLPF that has varying cut-off frequency according to change of the speed is designed on the frequency analysis result. The proposed method is verified by the experiment.

Design of Programmable Baseband Filter for Direct Conversion (Direct Conversion 방식용 프로그래머블 Baseband 필터 설계)

  • Kim, Byoung-Wook;Shin, Sei-Ra;Choi, Seok-Woo
    • Journal of Korea Multimedia Society
    • /
    • v.10 no.1
    • /
    • pp.49-57
    • /
    • 2007
  • Recently, CMOS RF integration has been widely explored in the wireless communication area to save cost, power, and chip area. The direct conversion architecture, rather than a more conventional super-het-erodyne, has been an attractive choice for single-chip integration because of its many advantages. However, the direct conversion architecture has several fundamental problems to solve in achieving performance comparable to a super-heterodyne counterpart. In this paper, we describe a programmable filter for mobile communication terminals using a direct conversion architecture. The proposed filter can be implemented with the active-RC filter and programmed to meet the requirements of different communication standards, including GSM, DECT and WCDMA. The filter can be tuned to select a detail frequency by changing the gate voltage of the MOS resistors. The gain of the proposed architecture can be programmed from 27dB to 72dB using the filter gain and VGA in 3dB steps.

  • PDF

A Current-Mode Analog Programmable EIR Filter for SDR Terminals

  • Shigehito Saigusa;Kim, Seong-Kweon;Shinji Ueda;Suguru Kameda;Hiroyuki Nakase;Kazuo Tsubouchi
    • Proceedings of the IEEK Conference
    • /
    • 2002.07a
    • /
    • pp.78-81
    • /
    • 2002
  • We propose a current-mode analog programmable finite-impulse-response (FIR) filter with variable tap circuits. From the circuit simulation, the operation of the 7- tap FIR filter is confirmed. We design and fabricate the 0.0625-step tap circuit using 0.8$\mu\textrm{m}$ CMOS technology. The proposed FIR filter has a variable length of taps and variable coefficients, so it has a potential for being used to software defined radio (SDR) terminals.

  • PDF

Implementation of efficient FIR filter using shift-and-add architecture and shared hardware (shift-and-add 구조와 연산 하드웨어 공유를 이용한 효율적인 FIR필터 구현)

  • 고방영;한호산;송태경
    • Proceedings of the IEEK Conference
    • /
    • 2002.06d
    • /
    • pp.183-186
    • /
    • 2002
  • In this paper, we present an area-efficient programmable FIR digital filter using canonic signed-digit(CSD) coefficients, in which the number of effective nonzero bits of each filter coefficient is reduced by sharing the shift and add logics for common nonzero bits between adjacent coefficients. Also, unused shift and add logics for a low- magnitude coefficient are reassigned to an appropriate high - amplitude coefficient. In consequence, the proposed architecture reduces the hardware area of a programmable FIR filter by about 24% and improves performance about 6-7dB compared to other multiplierless FIR filters with powers-of-two coefficients.

  • PDF

Dead Time Compensation and Polarity Check of Phase Currents Based on Programmable Low-pass Filter for Automotive Electric Drive Systems (자동차 전동 시스템을 위한 Programmable 저역 통과 필터 기반의 상전류 극성 판단 및 데드타임 보상)

  • Choi, Chinchul;Lee, Kangseok;Lee, Wootaik
    • Transactions of the Korean Society of Automotive Engineers
    • /
    • v.22 no.6
    • /
    • pp.23-30
    • /
    • 2014
  • This paper proposes a dead time compensation method for an AC motor drive using phase current polarity information which is detected based on a digital programmable low-pass filter (PLPF). The polarity detection using the PLPF is an alternative solution of a conventional method which uses a general low-pass filter (LPF) and hysteresis bands in order to avoid jittering due to noises. The PLPF not only adjusts its cutoff frequency according to the synchronous frequency of AC motors but also eliminates a gain attenuation and phase delay which are main problems of the general LPF. Through the PLPF, a fundamental component signal without gain and phase distortions is extracted from the measured raw current signal with noise. By use of the fundamental component, the polarity of current is effectively detected by reducing the hysteresis band. Finally, the proposed method compensates the dead time effects by adding or subtracting average voltage value to voltage references of the controller according to the detected current polarity information. The proposed compensation method is experimentally verified by compared with the conventional method.