• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.927-930
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• 2006

While Intel has been increasing its exclusive possession in the system IC semiconductor market, IBM, Sony, and Toshiba founded an alliance to develop the next entertainment multi-core processor, which is named CELL. Cell is designed upon the Power architecture and includes 8 SPE (Synergistic processor Element) cores for data handling, and supports SIMD architecture for optimal execution of multimedia, or game applications. Also, it includes expanded Power microarchitecture. In this paper, we analyzed and researched the Cell microprocessor, which is evaluated as the most powerful processor in this era.

• Journal of the Korean Institute of Intelligent Systems
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• v.20 no.3
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• pp.362-367
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• 2010

In this paper, we describe implementation of FPGA-based Nios II embedded processor system and linux device driver for image monitoring system which is supplement weakness for fixed surveillance area of existing CCTV system and by manual operation of the camera's moving. Altera Nios II processor 8.0 is supported MMU which is stable and efficient managed memory. We designed the image monitoring and control system by using Altera Nios II soft-core processor system which is flexible in various application and excellent adaptability. By implementation of camera device driver and VGA decvice driver for Linux-based Nios II system, we implemented image serveillance system for Nios II embedded processor system.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.11
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• pp.1707-1712
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• 2013

In this paper, we implement a hardware for motor control based on FPGA + embedded processor using Zynq EPP which is All Programmable SoC in order to improve a structural problem of motion control based on such as DSP, MCU and FPGA previously. The implemented motor controller that is fused controller with advantage of FPGA and embedded processor. The signal processing part of high velocity motor control is performed by motor controller based on FPGA. A motion profile and kinematic calculation that are required algorithm process such as operation of a complicate decimal point has processed in an embedded processor based on dual core. As a result of a hardware implementation, it has an advantage that has can be realized an effect of distribution process in one chip. It has also an advantage that is able to organize as a multi-axis motor controller through adding the IP core of motor control implemented on FPGA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.7
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• pp.52-60
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• 2010

In this paper, we propose a dynamic power management framework for multi-core systems. We reduced the power consumption of multi-core processors such as Intel Centrino Duo and ARM11 MPCore, which have been used at the consumer electronics and personal computer market. Each processor uses a different technique to save its power usage, but there is no embedded multi-core processor which has a precise power control mechanism such as dynamic voltage scaling technique. The proposed dynamic power management framework is suitable for smart phones which have an operating system to provide multi-processing capability. Basically, our framework follows an intuitive idea that reducing the power consumption of idle cores is the most effective way to save the overall power consumption of a multi-core processor. We could minimize the energy consumption used by idle cores with application-targeted policies that reflect the characteristics of active workloads. We defined some properties of an application to analyze the performance requirement in real time and automated the management process to verify the result quickly. We tested the proposed framework with popular processors such as Intel Centrino Duo and ARM11 MPCore, and were able to find that our framework dynamically reduced the power consumption of multi-core processors and satisfied the performance requirement of each program.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4A
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• pp.447-457
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• 2004

This paper proposes a RSA crypto-processor for embedded systems. The architecture of the RSA crypto-processor should be used relying on Big Montgomery algorithm, and is supported by configurable bit size. The RSA crypto-processor includes a RSA control signal generator, an optimal Big Montgomery processor(adder, multiplier). We use diverse arithmetic unit (adder, multiplier) algorithm. After we compared the various results, we selected the optimal arithmetic unit which can be connected with ARM core-processor. The RSA crypto-processor was implemented with Verilog HDL with top-down methodology, and it was verified by C language and Cadence Verilog-XL. The verified models were synthesized with a Hynix 0.25${\mu}{\textrm}{m}$, CMOS standard cell library while using Synopsys Design Compiler. The RSA crypto-processor can operate at a clock speed of 51 MHz in this worst case conditions of 2.7V, 10$0^{\circ}C$ and has about 36,639 gates.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.530-533
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• 2009

This paper proposes a method of recognizing that a person doesn't put on a safety cap using image processing method in DSP(Digital Signal Processor). It processes inputted images by image input devices that equipped in a industrial settings. If the method recognizes a person that doesn't put on a safety cap, a system transfers relevant recognition result to a supervisor and takes proper measures. If an accident happens and someone doesn't put on a safety cap, additional casualities could be. Proposed method can nip additional casualties in the bud. To recognize that a person don't put on a safety cap, images are processed by object abstraction, removal of noise, decision of a thing or a person, abstraction of a head part in a image, recognizing whether a man puts on a safety cap using HSV color space or not, and so on. Image input and image process are processed by DSP. And C language-based codes are optimized by an eignefunction(Intrinsics) for speed improvement of algorithms.

• Proceedings of the Korean Information Science Society Conference
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• 2000.10c
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• pp.18-20
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• 2000

디지털 음성통신을 위한 빠르고 쉬운 내장 프로세서(Embedded processor)가 요구되어짐에 따라 음성신호 압축 복원 알고리즘인 ADPCM과 LD-CELP의 구현에 가장 빈번히 사용되는 연산의 특성을 조사하였다. ARM6 processor core의 기본 구성요소들과 명령어집합을 기반으로 하여 음성부호화 알고리즘의 연산의 특성을 효율적으로 처리하기 위한 명령어와 구조를 추가한 범용 프로세서의 구조를 제안하고 VHDL로 기술하여 동작을 검증하였다. ARM6의 ALU logic에 leading zero count를 위한 회로를 추가하였고 opcode를 변경하였으며, LPC 계수 연산을 위해 제안된 MAC을 도입하여 효율적인 구현이 가능하도록 설계하였다.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.49 no.8
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• pp.514-521
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• 2000

This paper presents a direct thrust control scheme for permanent magnet linear synchronous motor(PMLSM) by using digital signal processor(DSP). And a simulation method for the direct thrust control of a permanent magnet linear synchronous motor using the equivalent circuit is presented. The detent force that was obtained by cubic spline method is considered in the simulation. Thrust correction coefficient is utilized to estimate actual thrust on the direct thrust control, which considers the longitudinal end effect due to the finite core length of the permanent magnet linear synchronous motor. The motor self inductance, the initial flux linkage by the permanent magnet is calculated in advance by the finite element analysis, and then the direct control simulation is carried out. As the results, thrust, current and speed are shwon.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.418-421
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• 2008

This paper presents the program to analyze an antenna for using the Moment Method. The program contains three different functional steps. In the first stage, the pre-processor is based on the Delaunay Triangulation Algorithm. The next stage, the main-processor, can be considered the core process of the program, which solutions are obtaining the linear matrix for using the Moment Method. The final stages, the name of the post-processor, analyze radiation patterns, which results are same with the S-parameters. The results demonstrate satisfactory agreement with the results for using other numerical packages and measurement data. We can confirm that the results of this program compare with the results of common program to analyze for an antenna.

• The Journal of the Korea Contents Association
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• v.8 no.9
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• pp.27-33
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• 2008

This paper designs Shared Memory on the Dual Core system so that it operates a general System V IPC on the Linux O.S. Shared Memory is the technique that many processes can access to identical memory area. We treat Shared Memory which is SVR in a kernel step. We design a share memory facility of Linux operating system on the Dual Core System. In this paper the suggesting of share memory facility design plan in Dual Core system is enhance the performance in existing an unity processor system as a dual core practical use. We attemp a performance enhance in each CPU for each process which uses a share memory.