• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.11
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• pp.1527-1535
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• 1995

This paper introduces an isolated word recognition system realized on a neurocomputer called E-MIND II, which is a 2-D torus wavefront array processor consisting of 256 DNP IIs. The DNP II is an all digital VLSI unit processor for the EMIND II featuring the emulation capability of more than thousands of neurons, the 40 MHz clock speed, and the on-chip learning. Built by these PEs in 2-D toroidal mesh architecture, the E- MIND II can be accelerated over 2 Gcps computation speed. In this light, the advantages of the E-MIND II in its capability of computing speed, scalability, computer interface, and learning are especially suitable for real time application such as speech recognition. We show how to map a TDNN structure on this array and how to code the learning and recognition algorithms for a user independent isolated word recognition. Through hardware simulation, we show that recognition rate of this system is about 97% for 30 command words for a robot control.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.4
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• pp.339-345
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• 2007

This paper presents a design of an FPGA (Field Programmable Gate Array) -based currentcontroller. Using the nature of the high computational capability of FPGA, the digital delay due to the algorithm execution can be reduced. The control performance can be better than the conventional DSP (Digital Signal Processor)-based current controller. Moreover, this method does not need any delay compensation algorithm because the digital delay is physically diminished. Therefore, the bandwidth of the current controller can be extended by this method. The feasibility of this method is verified by several experimental results under the various conditions.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.637-638
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• 2005

AAO templates were fabricated using a two-step anodization process with pretreatment such as electro polishing and annealing. To reduce process time and get well-aligned pore array, rapid thermal processor by an halogen lamp was employed in vacuum state at $500^{\circ}C$ for various time. The pore array of AAO template annealed at $500^{\circ}C$ for 2 h is comparable to a template annealed in conventional furnace at $500^{\circ}C$ for 30 h. The well-fabricated AAO template has the mean pore diameter of 70 nm, the barrierlayer thickness of 25 nm, and the pore depth of $9{\mu}m$. And the pore density can be as high as $2.0\times10^{10}cm^{-2}$.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.1
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• pp.49-55
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• 2007

To improved the multi-resolution fast hierarchical motion estimation by using de-interlacing algorithm that is effective in term of both performance and VLSI implementation, is proposed so as to cover large search area field-based as well as frame based image processing in SoC design. In this paper, we have simulated a various picture mode M=2 or M=3. As a results, the proposed algorithm achieved the motion estimation performance PSNR compare with the full search block matching algorithm, the average performance degradation reached to -0.7dB, which did not affect on the subjective quality of reconstructed images at all. And acquiring the more desirable to adopt design SoC for the fast hierarchical motion estimation, we exploit foreground and background search algorithm (FBSA) base on the dual arithmetic processor element(DAPE). It is possible to estimate the large search area motion displacement using a half of number PE in general operation methods. And the proposed architecture of MHME improve the VLSI design hardware through the proposed FBSA structure with DAPE to remove the local memory. The proposed FBSA which use bit array processing in search area can improve structure as like multiple processor array unit(MPAU).

• The KIPS Transactions:PartA
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• v.18A no.3
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• pp.99-108
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• 2011

Processor technology is currently continued to parallel processing techniques, not by only increasing clock frequency of a single processor due to the high technology cost and power consumption. In this paper, a SIMD (Single Instruction Multiple Data) based parallel processor is introduced that efficiently processes massive data inherent in multimedia. In addition, this paper proposes pixel subword parallel processing instructions for the SIMD parallel processor architecture that efficiently operate on the image and video pixels. The proposed pixel subword parallel processing instructions store and process four 8-bit pixels on the partitioned four 12-bit registers in a 48-bit datapath architecture. This solves the overflow problem inherent in existing multimedia extensions and reduces the use of many packing/unpacking instructions. Experimental results using the same SIMD-based parallel processor architecture indicate that the proposed pixel subword parallel processing instructions achieve a speedup of $2.3{\times}$ over the baseline SIMD array performance. This is in contrast to MMX-type instructions (a representative Intel multimedia extension), which achieve a speedup of only $1.4{\times}$ over the same baseline SIMD array performance. In addition, the proposed instructions achieve $2.5{\times}$ better energy efficiency than the baseline program, while MMX-type instructions achieve only $1.8{\times}$ better energy efficiency than the baseline program.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.2
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• pp.17-25
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• 2003

In this paper, a processor architecture is proposed based on the state space implementation technique for real time processing of 2-D discrete wavelet transform(DWT). It conducts 2-D DWT operations in consideration of row and column direction simultaneously, thus can reduce latency due to memory access for storing intermediate results. It is a VLSI architecture suitable for real time processing. The proposed architecture includes only four multipliers and four adders, and NK-N internal memory storage, where K denotes the length of filter. It has a small hardware complexity. Therefore it is very suitable architecture for real time, embedded applications such as web camera server. Since the processor is easily extended to array structure, it can be applied to various image processing applications.

• Journal of electromagnetic engineering and science
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• v.8 no.2
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• pp.52-58
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• 2008

This paper concerns with signal cancellation problem in a linearly constrained adaptive array processor in coherent environment. Alternate mainbeam nulling approach was proposed to prevent the signal cancellation phenomenon. The linearly constrained LMS algorithm with a unit gain constraint and that with a null constraint in the direction of the desired signal is alternately implemented to reduce the signal interaction between the desired signal and the interferences, which is the main cause of the signal cancellation. It is shown that the proposed method performs better than a conventional method.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.4
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• pp.628-635
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• 1990

This paper describes a new gate array layout system, HAN-LACAD-G(HANyang LAyout CAD system for Gate array). HAN-LACAD-G is composed of placer, global router, detailed router, and output processor. In placement design, initial placement is performed by repetitive clustering and min-cut partitioning followed by placement improvement using the concept of pairwise interchange. In global routing phase, pins are assigned in each channel considering the routing congestion estimation and overflows in feedthroughs are restricted. For the detailed routing, we use layer and three layer channel routing techniques. Layout results are displayed graphically and modified interactively by the user using the layout editor.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.1
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• pp.95-102
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• 2013

This paper covers nulling algorithm. In this algorithm, we assume that nulling points are already known. In general, nulling algorithm using matrix equation was utilized. But, this algorithm is pointed out that computational complexity is disadvantage. So, we choose gradient method to reduce the computational complexity. In order to further reduce the computational complexity, we propose approximate gradient method using characteristic of trigonometric functions. The proposed method has same performance compared with conventional method while having half the amount of computation when the number of antenna and nulling point are 20 and 1, respectively. In addition, we could virtually eliminate the trigonometric functions arithmetic. Trigonometric functions arithmetic cause a big problem in actual implementation like FPGA processor(Field Programmable gate array). By utilizing the above algorithm in a multi-cell environment, beamforming gain can be obtained and interference can be reduced at same time. By the above results, the algorithm can show excellent performance in the cell boundary.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.409-413
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• 2008

In this paper, we introduce a platform of advanced multiple antenna system based on orthogonal frequency-division multiplexing (OFDM). The advanced multiple antennas have beamforming gain using array antenna. In array antenna systems, received signal has phase delay caused distance of each antennas, therefore it should compensate with optimum weight vector which calculated by Lagrange algorithm. To implement the presented above procedures using Digital Signal Processor (DSP), we should fixed-point design. The performance of implemented platform is verified through MATLAB$^{(R)}$ simulations with various signal environments.