• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.2 s.93
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• pp.182-188
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• 2005

This paper presents an efficient technique for interference suppression in IEEE 802.11b WLAN systems. A linearly constrained adaptive array processor which may improve reception performance of WLAN device by reducing co-channel interference signal and multipath effects effectively was proposed. A spatial smoothing method is used to prevent cancellation of a desired signal in a coherent environment and also integral nulling method is employed to improve the array performance in indoor environment. It was shown that the integral nulling approach performed best while the spatial smoothing method performed better than linearly constrained array processing. The performance of the WLAN system may be improved by the proposed methods which reduce co-channel, coherent, and WPAN interferences effectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.369-378
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• 2003

This paper presents design and VLSI implementations of a reassembly processor for ATM/AAL. The assembly processor is responsible for processing ATM cells from the receive physical interface. It controls the transfer of the AAL payload to host memory and performs all necessary SAR and CPCS checks. We propose the improved structure of cell identification algorithm and smart scatter method for host memory management. The proposed cell identification algorithm quickly locates the appropriate reassembly VC table based on the received VPI./VCI channel value in the ATM header. The cell identification algorithm also allow complete freedom in assignment of VCI/VPI values. The reassembly processor uses a smart scatter method to write cell payload data to host memory. It maintains the scatter operation and controls the incoming DMA block during scatter DMA to host memory. The proposed reassembly processor can perform reassembly checks on AAL. OAM cell. For an AAL5 connection, only CPCS checks, including the CRC32, are performed. In this paper, we proposed a practical reassembly architecture. The design of reassembly processor has become feasible using 0.6${\mu}{\textrm}{m}$ CMOS gate array technology.

• The KIPS Transactions:PartC
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• v.8C no.1
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• pp.1-11
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• 2001

There are several traditional factors of software quality. Some of them are such as correctness, reliability, efficiency, compatibility, portability, etc. In addition to them, security is required as another factor of software quality nowadays because some application programs are used as a way to attack information systems by stack frame manipulation. Each processor has its own peculiar stack frame mechanism and C language uses the characteristics of them. This paper explains the concept of security problem caused by stack frame manipulation, and the stack frame mechanism of Pentium, Alpha and SP ARC processor in detail. And then it examines the effect of stack frame mechanism on the security of programs in C language.

• The Journal of the Acoustical Society of Korea
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• v.20 no.7
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• pp.94-100
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• 2001

When using a sample covariance matrix data in paucity of snapshots, adaptive matched field processing will have problem in inverting covariance matrix due to the rank deficiency. The general solutions are diagonal loading and eigenanalysis methods, but there is a significant bias in the power output. This paper presents a quantitative study of bias of power output and the performance of source localization through the simulation and the measured data analysis in fixed source case using the diagonal loading method for the minimum variance processor. Results show that the bias in power output is reduced and the performance of source localization is improved when the number of snapshots is greater than the number of array sensors.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.391-394
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• 2006

The paper deals with the experimental GNSS receiver built at the Czech Technical University for experiments with the real GNSS signal. The receiver is based on software defined radio architecture. Receiver consists of the RF front end and a digital processor based on programmable logic. Receiver RF front end supports GPS L1, L2, L5, WAAS/EGNOS, GALILEO L1, E5A, E5B signals as well as GLONASS L1 and L2 signals. The digital processor is based on Field Programmable Gate Array (FPGA) which supports embedded processor. The receiver is used for various experiments with the GNSS signals like GPS L1/EGNOS receiver, GLONASS receiver and investigation of the EGNOS signal availability for a land mobile user. On the base of experimental GNSS receiver the GPS L1, L2, EGNOS receiver for railway application was designed. The experimental receiver is also used in GNSS monitoring station, which is independent monitoring facility providing also raw monitoring data of the GPS, EGNOS and Galileo systems via internet.

• Journal of Broadcast Engineering
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• v.24 no.1
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• pp.182-185
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• 2019

This paper analyzes performances of modules in implementing a programmable multi-format video decoder. The goal of the proposed platform is the high-end Full High Definition (FHD) video decoder. The proposed multi-format video decoder consists of a reconfigurable processor, dedicated bit-stream co-processor, memory controller, cache for motion compensation, and flexible hardware accelerators. The experiments suggest performance baseline of modules for the proposed architecture operating at 300 MHz clock with capability of decoding HEVC bit-streams of FHD 30 frames per second.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.3
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• pp.198-206
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• 2011

This paper presents a new programmable compensation circuit (PCC) for a System-on-Chip (SoC). The PCC is integrated with $0.18-{\mu}m$ BiCMOS SiGe technology. It consists of RF Design-for-Testability (DFT) circuit, Resistor Array Bank (RAB) and digital signal processor (DSP). To verify performance of the PCC we built a 5-GHz low noise amplifier (LNA) with an on-chip RAB using the same technology. Proposed circuit helps it to provide DC output voltages, hence, making the RF system chain automatic. It automatically adjusts performance of an LNA with the processor in the SoC when it goes out of the normal range of operation. The PCC also compensates abnormal operation due to the unusual PVT (Process, Voltage and Thermal) variations in RF circuits.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1565-1567
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• 2004

Various defects are found in FPD (Flat Panel Display) manufacturing process. So detecting these defects early and reprocessing them is an important factor that reduces the cost of production. In this paper, the bare glass inspection system for the FPD which is the early process inspection system in the FPD manufacturing process is designed and implemented using the high performance and accuracy CCD line scan camera. For the preprocessing of the high speed line image data, the Image Processing Part (IPP) is designed and implemented using high performance DSP (Digital signal Processor), FIFO (First in First out), FPGA (Field Programmable Gate Array) and the Data Management and System Control part are implemented using ARM (Advanced RISC Machine) processor to control many IPP and cameras and to provide remote users with processed data. For evaluating implemented system, experiment environment which has an area camera for reviewing and moving shelf is made.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.5
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• pp.366-370
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• 2015

This paper proposes a method for improving a branch predictor for the extendable instruction set computer (EISC) processor. The original EISC branch predictor has several shortcomings: a small branch target buffer, absence of a global history, a one-bit local branch history, and unsupported prediction of branches following LERI, which is a special instruction to extend an immediate value. We adopt a G-share branch predictor and eliminate the existing shortcomings. We verified the new branch predictor on a field-programmable gate array with the Dhrystone benchmark. The newly proposed EISC branch predictor also accomplishes higher branch prediction accuracy than a conventional branch predictor.

• The Journal of the Acoustical Society of Korea
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• v.19 no.2
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• pp.68-72
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• 2000

Matched field processing technique is performed by considering complex underwater environments. Specially, the performance of minimum variance processor is greatly degraded by eigenvalue problem. In this paper, we propose the minimum variance matched field processor using shaping matrix. This shaping matrix makes that the input covariance matrix is invertible and enhances the desired acoustic source component. It was proved effectively range/depth localization of the proposed method with simulated data and vertical array data collected by NATO SACLANT Center north of the island of Elba off the Italian west coast.