• Journal of the Institute of Electronics and Information Engineers
• /
• v.54 no.6
• /
• pp.55-64
• /
• 2017

High-capacity, high-definition image applications need to process considerable amounts of data at high speed. Accordingly, users of these applications demand a high-speed parallel execution system. To increase the speed of a parallel execution system, Park (2004) proposed a technique, called MAMS (Multi-Access Memory System), to access data in several execution units without the conflict of parallel processing memories. Since then, many studies on MAMS have been conducted, furthering the technique to MAMS-PP16 and MAMS-PP64, among others. As a memory architecture for parallel processing, MAMS must be constructed in one chip; therefore, a method to achieve the identical functionality as the existing MAMS while minimizing the architecture needs to be studied. This study proposes a method of miniaturizing the MAMS architecture in which the architectures of the ACR (Address Calculation and Routing) circuit and MMS (Memory Module Selection) circuit, which deliver data in memories to parallel execution units (PEs), do not use the MMS circuit, but are constructed as one shift and conditional statements whose number is the same as that of memory modules inside the ACR circuit. To verify the performance of the realized architecture, the study conducted the processing time of the proposed MAMS-PP64 through an image correlation test, the results of which demonstrated that the ratio of the image correlation from the proposed architecture was improved by 1.05 on average.

• Journal of Information Processing Systems
• /
• v.16 no.3
• /
• pp.588-598
• /
• 2020

An alternative state estimation filtering algorithm is designed for continuous time systems with noises as well as control input. Two kinds of estimation filters, which have different measurement memory structures, are operated selectively in order to use both filters effectively as needed. Firstly, the estimation filter with infinite memory structure is operated for a certain continuous time system. Secondly, the estimation filter with finite memory structure is operated for temporarily uncertain continuous time system. That is, depending on the presence of uncertainty, one of infinite memory structure and finite memory structure filtered estimates is operated selectively to obtain the valid estimate. A couple of test variables and declaration rule are developed to detect uncertainty presence or uncertainty absence, to operate the suitable one from two kinds of filtered estimates, and to obtain ultimately the valid filtered estimate. Through computer simulations for a continuous time aircraft engine system with different measurement memory lengths and temporary model uncertainties, the proposed state estimation filtering algorithm can work well in temporarily uncertain as well as certain continuous time systems. Moreover, the proposed state estimation filtering algorithm shows remarkable superiority to the infinite memory structure filtering when temporary uncertainties occur in succession.

• Journal of Internet of Things and Convergence
• /
• v.9 no.1
• /
• pp.19-24
• /
• 2023

Recently, with the recent rapid development of memory technology, various types of memory are developed and are used to improve processing speed in data management systems. In particular, NAND flash memory is used as a main media for storing data in memory-based storage devices because it has a nonvolatile characteristic that it can maintain data even at the power off state. However, since the recently studied memory-based storage device consists of various types of memory such as MRAM and PRAM as well as NAND flash memory, research on memory management technology is needed to improve data processing performance and efficiency of media in a storage system composed of different types of memories. In this paper, we propose a memory mapping scheme thought technique for efficiently managing data in the storage device composed of various memories for data management. The proposed idea is a method of managing different memories using a single mapping table. This method can unify the address scheme of data and reduce the search cost of data stored in different memories for data tiering.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.3 no.2
• /
• pp.79-85
• /
• 2008

It is important to consider the life of battery and low power operation for various wireless communications. Thus, Analog current-mode signal processing with SI circuit has been taken notice of in designing the LSI for wireless communications. However, in current mode signal processsing, current memory circuit has a problem called clock-feedthrough. In this paper, we examine the connection of CMOS switch that is the common solution of clock-feedthrough and calculate the relation of width between CMOS switch for design methodology for improvement of current memory. As a result of simulation, when the width of memory MOS is 20um, ratio of input current and bias current is 0.3, the width relation in CMOS switch is obtained with $W_{Mp}=5.62W_{Mn}+1.6$, for the nMOS width of 2~6um in CMOS switch. And from the same simulation condition, it is obtained with $W_{Mp}=2.05W_{Mn}+23$ for the nMOS width of 6~10um in CMOS switch. Then the defined width relation of MOS transistor will be useful guidance in design for improvement of current memory.

• Sleep Medicine and Psychophysiology
• /
• v.24 no.2
• /
• pp.79-85
• /
• 2017

Targeted memory reactivation (TMR) is a method whereby cues associated with previous learning are used to externally reactivate aspects of this learning. Research findings demonstrate that TMR can be a useful tool to enhance memory consolidation during sleep in both animals and humans, especially in the declarative/spatial domain. Neurocognitive processing during sleep with covert cueing via auditory or olfactory stimulation can benefit memory storage. These beneficial effects on memory consolidation during sleep are associated with the activation of memory-related brain areas. The purpose of the present review is to provide a short overview of the findings of studies that adopted the TMR method of sleep-dependent memory consolidation and to suggest the potential applications of TMR in variable areas.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.15 no.12
• /
• pp.2632-2640
• /
• 2011

In this paper, we implemented a memory controller which can accommodate data processing blocks. The memory controller is arbitrated by the internal arbiter which receives request signals from masters and sends grant and data signals to masters. The designed memory controller consists of Master Interface, Master Arbitrator, Memory Interface, Memory accelerator. It was designed using VHDL, and verified using the memory model of SAMSING Inc. For FPGA synthesis and verification, Quartus II of ATERA Inc. was used. The target device is Cyclone II. For simulation, ModelSim of Cadence Inc was used.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.11 no.1
• /
• pp.57-61
• /
• 1998

In this study, PLZT stock solutions were prepared by Sol-Gel processing after the compositions were selected in the memory region of PLZT bulk phase diagram. PLZT solutions were deposited on the ITO glass substrate by spin-coating method. The thin films were annealed by rapid thermal processing. The electric characteristics, hysteresis loop, C-V characteristics of thin films in the memory region were measured in order to investigate the electrical characteristics of PLZT thin films. In selected compositions the decrease in Zr/Ti ratio led to an increase in dielectric constant and the decrease in remanent polarization and coercieve field which brought about slim hysteresis loop.

• Journal of KIISE:Databases
• /
• v.35 no.1
• /
• pp.67-83
• /
• 2008

In order to realize ubiquitous computing, it is essential to efficiently use the resources and the computing power of mobile devices. Among others, memory efficiency, energy efficiency, and processing efficiency are required in executing the softwares embedded in mobile devices. In this paper, query processing over XML data in a mobile device where resources are limited is addressed. In a device with limited amount of memory, the techniques of XML. stream query processing need to be employed to process queries over a large volume of XML data Recently, a technique Galled XFrag was proposed whereby XML data is fragmented with the hole-filler model and streamed in fragments for processing. With XFrag, query processing is possible in the mobile device with limited memory without reconstructing the XML data out of its fragment stream. With the hole-filler model, however, memory efficiency is not high because the additional information on holes and fillers needs to be stored. In this paper, we propose a new technique called XFLab whereby XML data is fragmented with the XML labeling scheme which is for representing the structural relationship in XML data, and streamed in fragments for processing. Through implementation and experiments, XML showed that our XFLab outperformed XFrag both in memory usage and processing time.

• Korean Journal of Cognitive Science
• /
• v.21 no.4
• /
• pp.697-723
• /
• 2010

Recent studies report that in terms of object memory, survival context has mnemonic advantage over other context conditions (e.g., Nairne et al, 2007). The present experiments explored whether this effect can also affect task-irreverent object location memory, and tested whether the context can change gender difference in object location memory. Participants were asked to rate the relevance of pictures presented at random locations (experiment 1) or words (experiment 2) under survival context or moving context. After rating the pictures or words, they answered recall test and location retrieval test. The results revealed higher accuracy in memory for objects encoded under survival context. Moreover, survival processing enhanced location memory, and the survival advantage in location memory emerged among woman.

• Journal of Positioning, Navigation, and Timing
• /
• v.12 no.1
• /
• pp.75-81
• /
• 2023

In this study, we design an optimized Graphics Processing Unit (GPU)-based GNSS signal processing technique with the goal of designing and implementing a GNSS Software Defined Receiver (SDR) that can operate in real time all-in-view mode under multi-constellation and multi-frequency signal environment. In the proposed structure the correlators of the existing GNSS SDR are processed by the GPU. We designed a memory structure and processing method that can minimize memory access bottlenecks and optimize the GPU memory resource distribution. The designed GNSS SDR can select and operate only the desired GNSS or desired satellite signals by user input. Also, parameters such as the number of quantization bits, sampling rate, and number of signal tracking arms can be selected. The computing capability of the designed GPU-based GNSS SDR was evaluated and it was confirmed that up to 2400 channels can be processed in real time. As a result, the GPU-based GNSS SDR has sufficient performance to operate in real-time all-in-view mode. In future studies, it will be used for more diverse GNSS signal processing and will be applied to multipath effect analysis using more tracking arms.