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http://dx.doi.org/10.6109/jkiice.2011.15.12.2632

VLSI Architecture of General-purpose Memory Controller for Multiple Processing  

Lee, Yoon-Hyuk (광운대학교)
Seo, Young-Ho (광운대학교)
Kim, Dong-Wook (광운대학교)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.15, no.12, 2011 , pp. 2632-2640 More about this Journal
Abstract
In this paper, we implemented a memory controller which can accommodate data processing blocks. The memory controller is arbitrated by the internal arbiter which receives request signals from masters and sends grant and data signals to masters. The designed memory controller consists of Master Interface, Master Arbitrator, Memory Interface, Memory accelerator. It was designed using VHDL, and verified using the memory model of SAMSING Inc. For FPGA synthesis and verification, Quartus II of ATERA Inc. was used. The target device is Cyclone II. For simulation, ModelSim of Cadence Inc was used.
Keywords
memory controller; multiple master; SDRAM; design; FPGA;
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  • Reference
1 Micron Technology, Inc. MT48LC8M32B2 SDRAM
2 S. Hosseini-Khayat and A. D. Bovopoulos, "A simple and efficient bus management scheme that supports continuous streams," ACM Trans. Comput. Syst., vol. 13, no. 2, pp. 122-140, 1995.   DOI   ScienceOn
3 J. Carter et al., ""Impulse: Building a smarter memory controller,"" in Proc. HPCA, Jan. 1999, pp. 70-79.
4 S. Rixner et al., ""Memory access scheduling,"" in Proc. ISCA, Vancouver, BC, Canada, Jun. 2000, pp. 128- 138.
5 B. Furht, "Multimedia systems: An overview," IEEE Multimedia, vol. 1, no. 1, pp. 47-59, Spring 1994.   DOI   ScienceOn
6 F. Catthoor et al., Custom Memory Management Methodology: Exploration of Memory Organization for Embedded Multimedia System Design. Norwell, MA: Kluwer, 1998.
7 John G. Ackenhusen, Real-time signal processing: Design and Implenentation of signal processing systems, Prentice Hall , pp. 290-319, 1999
8 유회준, "DRAM DESIGN," 홍릉과학출판사, 1996.