• Journal of Biosystems Engineering
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• v.26 no.2
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• pp.177-188
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• 2001

This research was carried out to examine the optimum design conditions of a vertical small-scale milling machine where the rough rice is processed directly into the white rice in one pass. Effects of the main spindle speed, feed screw pitch and ceramic coating length of the roller on various milling characteristics such as white rice processing capacity, electric energy consumption, rice temperature increase, broken rice ratio, moisture reduction, outlet force and crack ratio increase were studied. The results are as follows. 1. The maximum white rice processing capacity and the lowest crack ratio increase, were obtained from a machine with specification: main spindle speed of 970rpm having a feed screw pitch of 19㎜. 2. The minimum electric energy consumption was obtained with the main spindle speeds of 900 and 970rpm respectively having a feed screw pitch of 19㎜. 3. The rice temperature was increased as the feed screw pitch decreased and the main spindle speed increased. 4. Broken rice ratio was relatively low with the range of 0.8∼1.3%. 5. Moisture content loss was with the range of 0.05∼0.4%. 6. The highest outlet force was 0.72kg$\_$f/ with 900rpm of the main spindle speed and 19㎜ of the feed screw pitch and the lowest outlet force was 0.18∼0.34kg$\_$f/ with 970rpm of the main spindle speed and 16㎜ of the feed screw pitch. 7. The optimum design conditions for the vertical small-scale milling machine were obtained at 970rpm of the main spindle speed, 19㎜ of the feed screw pitch and 20㎜ of the ceramics coating length.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.341-352
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• 2012

This paper presents a Processing Engine (PE) which is used in Low Density Parity Codec (LDPC) application with a novel charge-recovery logic called pseudo-NMOS boost logic (pNBL), to achieve high-speed and low power dissipation. pNBL is a high-overdriven and low area consuming charge recovery logic, which belongs to boost logic family. Proposed Processing Engine is used in LDPC circuit to reduce operating power dissipation and increase the processing speed. To demonstrate the performance of proposed PE, a test chip is designed and fabricated with 0.18 2m CMOS technology. Simulation results indicate that proposed PE with pNBL dissipates only 1 pJ/cycle when working at the frequency of 403 MHz, which is only 36% of PE with the conventional static CMOS gates. The measurement results show that the test chip can work as high as 609 MHz with the energy dissipation of 2.1 pJ/cycle.

• Korean Chemical Engineering Research
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• v.56 no.3
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• pp.343-348
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• 2018

Each of the two polycarbonates (PC) of different molecular weights was blended with acrylonitrile-butadiene-styrene (ABS) under high-shear rate processing to afford PC/ABS. Sizes of ABS dispersed phases and mechanical properties of PC/ABS blends were investigated and high-shear rate processing of PC/ABS was carried out by changing screw speed and processing time. Prepared specimens were examined by scanning electron microscope (SEM) to observe morphology changes. Sizes of ABS dispersed phases in PC/ABS blends were observed to decrease gradually as screw speeds increased. Tensile strengths and elongations of specimens were investigated by universal testing method (UTM) to study the influence of molecular weight of PC exerting on PC/ABS blends. As a result, PC1/ABS blends (PC1: higher molecular weight PC) exhibited more strengthened properties than PC2/ABS (PC2: lower molecular weight PC). The tensile strength of PC1/ABS showed an increasing tendency when the screw speed increased, and the elongation did not show a significant decrease, but increased slightly with increasing shear time at a constant screw speed of 1000 rpm.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.11 no.1
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• pp.26-32
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• 2012

Polishing is one of the important methods in manufacturing of Si wafers and in thinning of completed device wafers. This study will report the characteristic of wafer according to processing time, machining speed and pressure which have major influence on the abrasion of Si wafer polishing. It is possible to evaluation of wafer abrasion by load cell and infrared temperature sensor. The characteristic of wafer surface according to processing condition is selected to use a result data that measure a pressure, machining speed, and the processing time. This result is appeared by the characteristic of wafer surface in machining condition. Through that, the study cans evaluation a wafer characteristic in variable machining condition. It is important to obtain optimal condition. Thus the optimum condition selection of ultra precision Si wafer polishing using load cell and infrared temperature sensor. To evaluate each machining factor, use a data through each sensor. That evaluation of abrasion according to variety condition is selected to use a result data that measure a pressure, machining speed, and the processing time. And optimum condition is selected by this result.

• Journal of the Optical Society of Korea
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• v.17 no.1
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• pp.68-72
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• 2013

We developed an SD-OCT (Spectral Domain-Optical Coherence Tomography) system which uses a GPU (Graphics Processing Unit) for processing. The image size from the SD-OCT system is $1024{\times}512$ and the speed is 110 frame/sec in real-time. K-domain linearization, FFT (Fast Fourier Transform), and log scaling were included in the GPU processing. The signal processing speed was about 62 ms using a CPU (Central Processing Unit) and 1.6 ms using a GPU, which is 39 times faster. We performed an in-vivo retinal scan, and reconstructed a 3D visualization based on C-scan images. As a result, there were minimal motion artifacts and we confirmed that tomograms of blood vessels, the optic nerve, and the optic disk are clearly identified. According to the results of this study, this SD-OCT can be applied to real-time 3D display technology, particularly auxiliary instruments for eye operations in ophthalmology.

• Journal of Korea Society of Industrial Information Systems
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• v.22 no.2
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• pp.61-70
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• 2017

In This Paper, the Classification Speed of Vehicle Headlight Modules is Improved by a CPU-based Parallel Processing Using OpenMP. Also, a Classification Method of Headlight Modules which Extracts their Features after Revising their Alignment is Proposed. To Analyze the Performance of the Proposed Method, the Discrimination Accuracy and the Processing Speed were Compared with the Method Using Gray Image and the Method Using Line Detection. As the Results of the Analysis, in the Discrimination Accuracy, the Proposed Method and the Line Detection Method Showed good Performance, but the Proposed Method Showed Better Performance than the Line Detection Method by the Processing Speed. Also, the Gray-based Method was the Best in Processing Speed, but the Proposed Method is Better than the Gray-based Method in the Discrimination Accuracy.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.11
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• pp.1135-1141
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• 2014

Performing wideband DDC while quantizing signal over a wide dynamic range and high speed sampling rate have primarily been implemented in a hardware such as, FPGA or ASIC because of time-consuming job. Real-time wideband DDC SW, even though signal environment changes, adapt to signal environment flexibly and can be reused. In addition, it has a lower price than the hardware implementation. In this paper, we study the system design that can be stored in real time designing a high-speed parallel processing architecture for SW-based wideband DDC. Finally, applying a Ping-Pong Buffering mechanism for receiving a signal in real time and CUDA for a high-speed signal processing, we verify wideband DDC design procedure that meets the signal processing.

• Journal of Institute of Control, Robotics and Systems
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• v.5 no.6
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• pp.691-697
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• 1999

This paper describes the implementation of a high speed image processing board. This image processing board is consist of a image acquisition part and a image processing part. The image acquistion part is digitizing the image input data from CIS and save it to the dual port RAM. By putting on the dual port memory between two parts, during acquistion of image, the image processing part can be effectively processing of large-volume image data. Most of all image preprocessing part are integrated in a large-scaled FPGA. We arwe using ADSP-2181 of the Analog Device Inc., LTD. for a image processing part, and using the available all memory of DSP for the large-volume image data. Especially, using of IDMA exchanges the data with the external microprocessor or the external PC, and can watch the result of image processing and acquired image. Finally, we show that an implemented image processing board used for the simulation of image retreval by the one of the typical application.

• Journal of Mechanical Science and Technology
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• v.16 no.8
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• pp.1033-1038
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• 2002

Genetic alsorithm (GA) , compared to the gradient-based optimization, has advantages of convergence to a global optimized solution. The genetic algorithm requires so many number of analyses that may cause high computational cost for genetic search. This paper proposes a personal computer network programming based on TCP/IP protocol and client-server model using socket, to improve processing speed of the genetic algorithm for optimization of composite laminated structures. By distributed processing for the generated population, improvement in processing speed has been obtained. Consequently, usage of network-based genetic algorithm with the faster network communication speed will be a very valuable tool for the discrete optimization of large scale and complex structures requiring high computational cost.

• Journal of the Korean Ceramic Society
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• v.46 no.1
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• pp.30-34
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• 2009

A Sand blasting technology has been used to address via and trench processing of glass wafer of optic semiconductor packaging. Manufactured sand blast that is controlled by blast nozzle and servomotor so that 8" wafer processing may be available. 10mm sq test device manufactured by Dry Film Resist (DFR) pattern process on 8" glass wafer of $500{\mu}m's$ thickness. Based on particle pressure and the wafer transfer speed, etch rate, mask erosion, and vertical trench slope have been analyzed. Perfect 500 um tooling has been performed at 0.3 MPa pressure and 100 rpm wafer speed. It is particle pressure that influence in processing depth and the transfer speed did not influence.