• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.66-79
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• 2008

Several oxides have recently been reported to have resistance-switching characteristics for nonvolatile memory (NVM) applications. Both binary and ternary oxides demonstrated great potential as resistive-switching memory elements. However, the switching mechanisms have not yet been clearly understood, and the uniformity and reproducibility of devices have not been sufficient for gigabit-NVM applications. The primary requirements for oxides in memory applications are scalability, fast switching speed, good memory retention, a reasonable resistive window, and constant working voltage. In this paper, we discuss several materials that are resistive-switching elements and also focus on their switching mechanisms. We evaluated non-stoichiometric polycrystalline oxides ($Nb_2O_5$, and $ZrO_x$) and subsequently the resistive switching of $Cu_xO$ and heavily Cu-doped $MoO_x$ film for their compatibility with modem transistor-process cycles. Single-crystalline Nb-doped $SrTiO_3$ (NbSTO) was also investigated, and we found a Pt/single-crystal NbSTO Schottky junction had excellent memory characteristics. Epitaxial NbSTO film was grown on an Si substrate using conducting TiN as a buffer layer to introduce single-crystal NbSTO into the CMOS process and preserve its excellent electrical characteristics.

• Journal of the Korean Vacuum Society
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• v.21 no.6
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• pp.354-361
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• 2012

The organic memory device was made by the plasma polymerization method which was not the dry process but the wet process. The memory device consist of the styrene and MMA monomer as the insulating layer, MMA monomer as the tunneling layer and Au thin film as the memory layer which was fabricated by thermal evaporation method. The I-V characteristics of fabricated memory device got the hysteresis voltage of 27 V at 40/-40 V double sweep measuring conditions. At this time, the optimized structure was 7 nm of Au thin film as floating gate, 400 nm of styrene thin film as insulating layer and 30 nm of MMA thin film as tunneling layer. Therefore we got the charge trapping characteristics by the hysteresis voltage. From the paper, styrene indicated a good charge trapping characteristics better than MMA. In the future, we expect to make devices by using styrene thin film rather than Au thin film.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.1
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• pp.77-82
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• 2014

SD memory cards are widely used in portable digital devices, and most of them exploit NAND flash memory as their storage, so that they have a feature of storing users' important data safely with low costs. In case of using NAND flash memory as storage, however, there is no method to store users' data if memory capacity is insufficient when transferring a large volume of data. This paper proposes a virtual SD memory card system. It used a SD memory card device driver to process data requested from a host by exploiting external storage rather than by exploiting flash memory as a memory core for storing data to the SD memory card. For experiment, it used the FPGA-based SD card slave controller IP on the SMC controller with a S3C2450 ARM CPU to test.

• Journal of Korea Spatial Information System Society
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• v.11 no.2
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• pp.79-88
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• 2009

The volume of memory to store real-time data stream is varied dynamically. Continuous queries processing the data stream must manage the storage volume dynamically. In previous research, according to current volume of data a general memory manager which allocates and releases memory by a page unit is researched.However, the method frequently executes page allocation and release to store data stream. Moreover, particularly delayed queries can monopolize many of pages because the method directly allocates pages when a query has not enough memory. Focusing on the problems in memory management systems, this research proposes a memory management method which reduces the frequency of allocation and release and uniformly distributes pages for queries. The method can reduce the frequency of allocation and release through allocation based on utilization ratio of pages in each query and prevent memory monopoly through memory allocation which considers query delay.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.72-85
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• 2007

The development of memory design and process technology enabled the production of high density memory. However, this increased the complexity of the memory making memory testing more complicated, and as a result, it brought about an increase in memory testing costs. Effective memory test algorithm must detect various types of defects within a short testing time, and especially in the case of port memory test algorithm, it must be able to detect single port memory defects, and all the defects in the dual port memory. The March A2PF algorithm proposed in this paper is an effective test algorithm that detects all types of defects relating to the duel port and single port memory through the short 18N test pattern.

• Sleep Medicine and Psychophysiology
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• v.4 no.1
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• pp.15-28
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• 1997

Longterm memory is encoded in the neuronal connectivities of the brain. The most successful models of human memory in their operations are models of distributed and self-organized associative memory, which are founded in the principle of simulaneous convergence in network formation. Memory is not perceived as the qualities inherent in physical objects or events, but as a set of relations previously established in a neural net by simultaneousy occuring experiences. When it is easy to find correlations with existing neural networks through analysis of network structures, memory is automatically encoded in cerebral cortex. However, in the emergence of informations which are complicated to classify and correlated with existing networks, and conflictual with other networks, those informations are sent to the subcortex including hippocampus. Memory is stored in the form of templates distributed across several different cortical regions. The hippocampus provides detailed maps for the conjoint binding and calling up of widely distributed informations. Knowledge about the distribution of correlated networks can transform the existing networks into new one. Then, hippocampus consolidats new formed network. Amygdala may enable the emotions to influence the information processing and memory as well as providing the visceral informations to them. Cortico-striatal-pallido-thalamo-cortical loop also play an important role in memory function with analysis of language and concept. In case of difficulty in processing in spite of parallel process of informations, frontal lobe organizes theses complicated informations of network analysis through temporal processing. With understanding of brain mechanism of memory and information processing, the brain mechanism of mental phenomena including psychopathology can be better explained in terms of neurobiology and meuropsychology.

• Journal of the Korean Society of Costume
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• v.52 no.4
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• pp.141-154
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• 2002

The purpose of this study was to define 'sponsorship' as a kind of advertising tool, and to describe its effects on consumer brand attitude and actual purchase behavior. From previous research results, clothing sponsorship was defined as 'indirect advertisement', which has common ad traits as well as the uncommon ad traits, such as indirectness, emotional affinity, and symbolism. Results from empirical research using 1,227 data collected in Seoul and Kyounggi Areas were as follows ; (1) Television drama clothing sponsorship was proved to have effects on brand image, emotional & rational brand attitudes, decision making process, and actual purchase behavior. (2) Each of drama clothing sponsorship factors, such as 'drama', 'role', and 'actress', had different effects on brand memory and attitudes. (3) Consumer decision making process initiated by drama clothing sponsorship followed two different processes, which were called 'rational' and 'heuristic'. The rational process followed every steps of EKB model, which explained consumer's rational shopping, but heuristic model was closer to emotional and impulsive shopping.

• Journal of the Korea Society for Simulation
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• v.11 no.3
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• pp.49-58
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• 2002

It takes 2 or 3 months to manufacture memory device. Defect has to exist owing to hundreds of processes. If there are too many defects, the memory has to be rejected. But if there are a few defects, it will be more efficient and cost reducing for the company to use it by repairing. Therefore, laser-repair process is needed for such a reason and redundancy analysis is needed to establish correct target of laser-repair process. The equipment development company had provided the redundancy analysis and each development company had developed and provided separately. So, to analyze the similar type of defects, redundancy analysis time can be very different by the manufacture. The purpose of this research is to strengthen the competitive price and to apply correlation concept in business for reducing the redundancy analysis time to repair the defects

• The Transactions of the Korean Institute of Electrical Engineers
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• v.38 no.3
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• pp.237-246
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• 1989

A sliding memory covariance circular lattice (SMC-CL) filter and an efficient ARMA modeling method using the SMC-CL filter are presented. At first, SMC-CL filter is derived based on the geometric approach. Then ARMA process is converted into 2 channel AR process, and SMC-CL filter is applied to it. The structure of SMC-CL filter becomes simpler in case of ARMA modeling due to the whiteness of a driving input process. The parameters of ARMR process can be obtained by the Levinson recursions from the PARCOR coefficients of the second channel of the filter. Computer simulations are performed to show the effctiveness of the proposed algorithm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.196-203
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• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.