• 한국통신학회논문지
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• 제29권8C호
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• pp.1113-1124
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• 2004

본 논문에서는 입력 영상을 실시간으로 압축 및 복원할 수 있는 하드웨어(hardware, H/W)의 구조를 제안하고 처리되는 영상의 보안 및 보호를 위한 워터마킹 기법(watermarking)을 제안하여 H/W로 내장하고자 한다. 영상압축과 복원과정을 하나의 FPGA 칩 내에서 처리할 수 있도록 요구되는 모든 영상처리 요소를 고려하였고 VHDL(VHSIC Hardware Description Language)을 사용하여 각각을 효율적인 구조의 H/W로 사상하였다. 필터링과 양자화 과정을 거친 다음에 워터마킹을 수행하여 최소의 화질 감소를 가지고 양자화 과정에 의해 워터마크의 소실이 없으면서 실시간으로 동작이 가능하도록 하였다. 구현된 하드웨어는 크게 데이터 패스부(data path part)와 제어부(Main Controller, Memory Controller)로 구분되고 데이터 패스부는 영상처리 블록과 데이터처리 블록으로 나누어진다. H/W 구현을 위해 알고리즘의 기능적인 간략화를 고려하여 H/W의 구조에 반영하였다. 동작은 크게 영상의 압축과 복원과정으로 구분되고 영상의 압축 시 대기지연 시간 없이 워터마킹이 수행되며 전체 동작은 A/D 변환기에 동기하여 필드단위의 동작을 수행한다. 구현된 H/W는 APEX20KC EP20K600CB652-7 FPGA 칩에서 69%(16980개)의 LAB(Logic Array Block)와 9%(28352개)의 ESB(Embedded System Block)을 사용하였고 최대 약 82MHz의 클록주파수에서 안정적으로 동작할 수 있어 초당 67필드(33 프레임)의 영상에 대해 워터마킹과 압축을 실시간으로 수행할 수 있었다.

• 한국GIS학회:학술대회논문집
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• 한국GIS학회 2003년도 공동 춘계학술대회 논문집
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• pp.472-477
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• 2003

멸종위기종의 서식지를 효율적으로 관리하기 위해서는 해당 종의 서식 가능한 지역의 분포를 알아야 한다. 본 연구의 목적은 GIS와 퍼지집합을 이용하여 산양(Nemorhaedus caudatus)의 서식지적합성모형을 개발하여 멸종 위기종의 서식지를 관리하기 위한 정보를 제공하는 것이다. 산양의 서식지적합성모형 개발을 위한 본 연구의 주요내용은 다음과 같다. 첫째, 산양 서식지 이용에 관한 기존 연구를 바탕으로 산양의 잠재적 서식지 환경변수를 분류하였으며, 분석 대상지의 산양 흔적 조사를 통해 서식지 환경변수의 재분류 및 x²검정(Chi-square test)을 통한 변수들의 유용성을 파악하고, 쌍체비교를 통한 환경변수별 가중치를 계산하였다. 둘째, 기존 부울논리(boolean logic)의 단점을 보완하기 위해 현장 조사의 결과를 바탕으로 퍼지논리(fuzzy logic)에 의한 산양 서식지의 각 환경변수별 주제도를 작성하고, 주제도들의 상관관계를 분석하여 상호 관련성이 높은 변수들의 중복을 피하였다. 셋째, 환경변수별 주제도와 변수별 가중치를 바탕으로 다기준평가기법(MCE, Multi-Criteria Evaluation)을 이용하여 분석대상지의 산양 서식지적합성모형을 개발하였다. 마지막으로, 개발된 서식지적합성모형의 타당성을 검증하기 위해 분석대상지 외부 지역을 대상으로 검증을 실시하였다. 분석 결과 분석대상지의 분류정확도는 서식가능성 0.5를 기준으로 93.94%의 매우 높은 분류정확도를 나타내었으며, 검증대상지에서는 95.74%의 분류정확도를 나타내어 본 모형의 분류정확도는 일관성이 높은 것으로 판단되었다. 또한 전체 공원구역에서 서식가능성 0.5이상의 면적은 59%를 차지하였다.퇴적이 우세한 것으로 관측되었다.보체계의 구축사업의 시각이 행정정보화, 생활정보화, 산업정보화 등 다양한 분야와 결합하여 보다 큰 시너지 효과와 사용자 중심의 서비스 개선을 창출할 수 있는 기반을 제공할 것을 기대해 본다.. 이상의 결과를 종합해볼 때, ${\beta}$-glucan은 고용량일 때 직접적으로 또는 $IFN-{\gamma}$ 존재시에는 저용량에서도 복강 큰 포식세로를 활성화시킬 뿐 아니라, 탐식효율도 높임으로써 면역기능을 증진 시키는 것으로 나타났고, 그 효과는 crude ${\beta}$-glucan의 추출조건에 따라 달라지는 것을 알 수 있었다.eveloped. Design concepts and control methods of a new crane will be introduced in this paper.and momentum balance was applied to the fluid field of bundle. while the movement of′ individual material was taken into account. The constitutive model relating the surface force and the deformation of bundle was introduced by considering a representative prodedure that stands for the bundle movement. Then a fundamental equations system could be simplified considering a steady state of the process. O

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.515-519
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• 2004

A Propeller-Anemometer is an instrument used specifically, to measure the wind speed. The accurate measurement of the wind speed is vitally important such required by any weather stations. In this research, the measurand of the instrumentation was the rotational speed of the propeller and the instrumentation result or output data was wind velocity. The speed measured was recorded digitally in the computer by using specific software. A specific sensor used to measure a variable by converting information of the variable (rotational speed of the propeller) into a dependent signal such as electrical signal in form of voltage. The development of Propeller-Anemometer involved few sets of instrumentation process and equipment. It included three major parts, mechanical, electronics and computer. The main instrumentation processes were physical and signal interfacing, signal conditioning, logic interfacing, data transmission to computer and processing the data. Generally, this paper presents the overall concept and design of Propeller-Anemometer Instrumentation. However, an emphasis was mainly in designing and building the interfacing system, hardware and software. Basically, for the first phase of the development, this project designed and built the RS232 terminal using Peripheral Interface Controller (PIC), PIC16F873. The hardware can be interfaced to computer or other compatible devices. This routine converted input voltage from the circuit to speed (velocity) and transmitted them afterwards to the target device by using the RS232 transmission protocol. This implementation implied a computer display as visual interface. For the purpose of this paper, RS232 data transmission was carried out using a Microsoft Visual Basic software routine.

• 대한전기학회논문지:시스템및제어부문D
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• 제53권1호
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• pp.1-9
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• 2004

In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into a H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel for the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks. The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit or a field synchronized with the A/D converter. The implemented H/W used the 54％(12943) LAB(Logic Array Block) and 9％(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation. that is. processing 60 fields/sec(30 frames/sec).

• 대한전자공학회논문지
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• 제27권3호
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• pp.108-115
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• 1990

고속 퓨리어변화(Fast Fourier Transform)연산용 2차원 시스토릭 어레이의 기본 구성요소인 단위 처리요소(Unit processing element)를 직접회로로 설계, 제작하고 제작된 칩을 평가하였다. 설계된 칩은 FFT 연산을 위한 데이타셔플링 기능과 반쪽 버터플라이 연산기능을 수행한다. 약 6,500여개의 트랜지스터로 구성된 이 칩은 표준셀 방식으로 설계되었으며, 2미크론 이중 금속 P-Well CMOS 공정으로 제작되었다. 제작된 칩을 웨이퍼 상태로 프로브카드를 이용하여 평가하였으며 그 결과, 20MHz 클럭 주파수에서 반쪽 버터플라이 연산이 0.5${\mu}sec$에 수행됨을 확인하였다. 본 논문에서 설계, 제작된 칩을 이용하여 1024-point FFT를 연산하는 경우 11.2${\mu}sec$의 시간이 소요될 것으로 예상된다.

• 보건교육건강증진학회지
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• 제27권4호
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• pp.165-175
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• 2010

Objectives: The purpose of this study is to evaluate the program theory of a lifestyle intervention program for the prevention and treatment of metabolic syndrome. Methods: The program evaluated is a tailored intervention for multiple health behavior associated with metabolic syndrome which is informed by theoretical constructs from the Intervention Mapping and Transtheoretical model. The program components include one-to-one health counseling, a self-management handbook, and a health diary. To evaluate program impact theory we examined the logic of program goals and objectives, intervention methods and strategies, and the theoretical constructs of program materials through document review and matrix building. Results: This evaluation has found that the intervention program applied social cognitive theory constructs to design intervention methods and strategies in addition to the Transtheoretical model: self-monitoring for goal setting and monitoring skill, outcome expectation for the benefits of health behavior change, and interaction with environment for observational learning through modeling. While the intervention addresses multiple determinants and behaviors, it is limited to an individual level and lacks social and environmental approaches. Following the Transtheoretical framework, the contents of the intervention materials were developed utilizing consciousness raising as a main strategy for earlier stages of change, and counterconditioning and stimulus control for later stages of change. Conclusion: Program theory evaluation can be a process of enhancing program validity. It would also be necessary for providing basis for efficient program implementation. When comparisons of program theory between similar programs are possible, program theory and validity will be strengthened when comparisons of program theories between similar programs are possible.

• 대한전자공학회논문지
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• 제25권9호
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• pp.1115-1124
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• 1988

A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.

• 전기전자학회논문지
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• 제24권1호
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• pp.319-325
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• 2020

본 논문에서 모바일 기기에 적용하는 DCM DC-DC 벅 변환기를 설계하였다. 이 변환기는 안정된 동작을 위한 보상기, PWM 로직과 파워 스위치로 구성되어 있다. 작은 하드웨어 폼-팩터를 얻기 위하여 칩 외부에서 사용하는 소자의 갯수를 최소화하여야 하며 이는 효율적인 주파수 보상과 디지털 스타트-업 회로로 구현하였다. 매우 작은 부하 전류에서 효율의 감소를 막기 위하여 버스트-모드 동작도 구현하였다. DCM 벅 변환기는 0.18um BCDMOS 공정으로 제작되었다. 2.8~5V의 입력 전압 범위에 대하여 출력 전압 값은 외부 저항 소자를 사용하여 1.8V로 프로그램 되었다. 1MHz의 스위칭 주파수 및 100mA의 부하 전류에서 측정된 최대 효율은 92.6%이다.

• 한국컴퓨터정보학회논문지
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• 제26권2호
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• pp.69-78
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• 2021

본 논문은 프라이빗(허가형) 블록체인을 이용한 인적자원 풀(Pool) 채용 시스템의 구현 방안에 대해서 다룬다. 인적자원(Human Resource)라는 용어가 보편적으로 사용되고 있고, 인력을 자원으로 인식하게 되었다. 이러한 변화에도 불구하고 인적자원 풀의 활용은 부진하다. 한번 입력된 정보는 주기적으로 갱신되지 않는 경우가 많고 공유, 검색, 경력관리 그리고 위변조 방지를 제공하지 않는다. 본 연구에서는 프라이빗(허가형) 블록체인을 활용한 인적자원 풀 채용시스템의 제안을 위해 첫 번째, 블록체인 네트워크를 이용하여 인적자원 풀(Pool)의 공유와 검색을 가능하게 하였고, 키워드를 사용하여 특정 조건을 만족하는 결과를 얻을 수 있도록 하였다. 두 번째, 입력되는 데이터의 무결성을 보장하기 위해 기관의 검증 프로세스 추가와 위·변조 방지를 위한 블록체인의 구조적 특성 활용하여 기술 외적인 부분으로 방지 대책을 마련하였다. 세 번째, 블록체인과 사전에 정의된 프로세스와 비즈니스 로직을 3개의 그룹이 각각 제어할 수 있게 Web UI를 포함하는 Dapp(Decentralized application)을 설계 및 구현 하였다.