• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1113-1124
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• 2004

In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel fur the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit of a field synchronized with the A/D converter. The implemented H/W used the 69%(16980) LAB(Logic Array Block) and 9%(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation of 60 fields/sec(30 frames/sec).

• Proceedings of the Korean Association of Geographic Inforamtion Studies Conference
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• 2003.04a
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• pp.472-477
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• 2003

멸종위기종의 서식지를 효율적으로 관리하기 위해서는 해당 종의 서식 가능한 지역의 분포를 알아야 한다. 본 연구의 목적은 GIS와 퍼지집합을 이용하여 산양(Nemorhaedus caudatus)의 서식지적합성모형을 개발하여 멸종 위기종의 서식지를 관리하기 위한 정보를 제공하는 것이다. 산양의 서식지적합성모형 개발을 위한 본 연구의 주요내용은 다음과 같다. 첫째, 산양 서식지 이용에 관한 기존 연구를 바탕으로 산양의 잠재적 서식지 환경변수를 분류하였으며, 분석 대상지의 산양 흔적 조사를 통해 서식지 환경변수의 재분류 및 x²검정(Chi-square test)을 통한 변수들의 유용성을 파악하고, 쌍체비교를 통한 환경변수별 가중치를 계산하였다. 둘째, 기존 부울논리(boolean logic)의 단점을 보완하기 위해 현장 조사의 결과를 바탕으로 퍼지논리(fuzzy logic)에 의한 산양 서식지의 각 환경변수별 주제도를 작성하고, 주제도들의 상관관계를 분석하여 상호 관련성이 높은 변수들의 중복을 피하였다. 셋째, 환경변수별 주제도와 변수별 가중치를 바탕으로 다기준평가기법(MCE, Multi-Criteria Evaluation)을 이용하여 분석대상지의 산양 서식지적합성모형을 개발하였다. 마지막으로, 개발된 서식지적합성모형의 타당성을 검증하기 위해 분석대상지 외부 지역을 대상으로 검증을 실시하였다. 분석 결과 분석대상지의 분류정확도는 서식가능성 0.5를 기준으로 93.94%의 매우 높은 분류정확도를 나타내었으며, 검증대상지에서는 95.74%의 분류정확도를 나타내어 본 모형의 분류정확도는 일관성이 높은 것으로 판단되었다. 또한 전체 공원구역에서 서식가능성 0.5이상의 면적은 59%를 차지하였다.퇴적이 우세한 것으로 관측되었다.보체계의 구축사업의 시각이 행정정보화, 생활정보화, 산업정보화 등 다양한 분야와 결합하여 보다 큰 시너지 효과와 사용자 중심의 서비스 개선을 창출할 수 있는 기반을 제공할 것을 기대해 본다.. 이상의 결과를 종합해볼 때, ${\beta}$-glucan은 고용량일 때 직접적으로 또는 $IFN-{\gamma}$ 존재시에는 저용량에서도 복강 큰 포식세로를 활성화시킬 뿐 아니라, 탐식효율도 높임으로써 면역기능을 증진 시키는 것으로 나타났고, 그 효과는 crude ${\beta}$-glucan의 추출조건에 따라 달라지는 것을 알 수 있었다.eveloped. Design concepts and control methods of a new crane will be introduced in this paper.and momentum balance was applied to the fluid field of bundle. while the movement of′ individual material was taken into account. The constitutive model relating the surface force and the deformation of bundle was introduced by considering a representative prodedure that stands for the bundle movement. Then a fundamental equations system could be simplified considering a steady state of the process. O

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.515-519
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• 2004

A Propeller-Anemometer is an instrument used specifically, to measure the wind speed. The accurate measurement of the wind speed is vitally important such required by any weather stations. In this research, the measurand of the instrumentation was the rotational speed of the propeller and the instrumentation result or output data was wind velocity. The speed measured was recorded digitally in the computer by using specific software. A specific sensor used to measure a variable by converting information of the variable (rotational speed of the propeller) into a dependent signal such as electrical signal in form of voltage. The development of Propeller-Anemometer involved few sets of instrumentation process and equipment. It included three major parts, mechanical, electronics and computer. The main instrumentation processes were physical and signal interfacing, signal conditioning, logic interfacing, data transmission to computer and processing the data. Generally, this paper presents the overall concept and design of Propeller-Anemometer Instrumentation. However, an emphasis was mainly in designing and building the interfacing system, hardware and software. Basically, for the first phase of the development, this project designed and built the RS232 terminal using Peripheral Interface Controller (PIC), PIC16F873. The hardware can be interfaced to computer or other compatible devices. This routine converted input voltage from the circuit to speed (velocity) and transmitted them afterwards to the target device by using the RS232 transmission protocol. This implementation implied a computer display as visual interface. For the purpose of this paper, RS232 data transmission was carried out using a Microsoft Visual Basic software routine.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.1
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• pp.1-9
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• 2004

In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into a H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel for the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks. The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit or a field synchronized with the A/D converter. The implemented H/W used the 54％(12943) LAB(Logic Array Block) and 9％(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation. that is. processing 60 fields/sec(30 frames/sec).

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.3
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• pp.108-115
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• 1990

This paper describes the design and fabrication of a processing element that will be used as a component in the construction of a two dimensional systolic for FFT. The chip performs data shuffling and radix-2 decimation-in-time (DIT) butterfly arithmetic. It consists of a data routing unit, internal control logic and HBA unit which computes butterfly arithmetic. The 6.5K transistors processing element designed with standard cells has been fabricated with a 2u'm double metal CMOS process, and evaluated by wafer probing measurements. The measured characteristics show that a HBA can be computed in 0.5 usec with a 20MHz clok, and it is estimated that the FFT of length 1024 can be transformed in 11.2 usec.

• Korean Journal of Health Education and Promotion
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• v.27 no.4
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• pp.165-175
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• 2010

Objectives: The purpose of this study is to evaluate the program theory of a lifestyle intervention program for the prevention and treatment of metabolic syndrome. Methods: The program evaluated is a tailored intervention for multiple health behavior associated with metabolic syndrome which is informed by theoretical constructs from the Intervention Mapping and Transtheoretical model. The program components include one-to-one health counseling, a self-management handbook, and a health diary. To evaluate program impact theory we examined the logic of program goals and objectives, intervention methods and strategies, and the theoretical constructs of program materials through document review and matrix building. Results: This evaluation has found that the intervention program applied social cognitive theory constructs to design intervention methods and strategies in addition to the Transtheoretical model: self-monitoring for goal setting and monitoring skill, outcome expectation for the benefits of health behavior change, and interaction with environment for observational learning through modeling. While the intervention addresses multiple determinants and behaviors, it is limited to an individual level and lacks social and environmental approaches. Following the Transtheoretical framework, the contents of the intervention materials were developed utilizing consciousness raising as a main strategy for earlier stages of change, and counterconditioning and stimulus control for later stages of change. Conclusion: Program theory evaluation can be a process of enhancing program validity. It would also be necessary for providing basis for efficient program implementation. When comparisons of program theory between similar programs are possible, program theory and validity will be strengthened when comparisons of program theories between similar programs are possible.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.9
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• pp.1115-1124
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• 1988

A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.

• Journal of IKEEE
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• v.24 no.1
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• pp.319-325
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• 2020

In this paper, a discontinuous-conduction mode (DCM) DC-DC buck converter is presented for mobile device applications. The buck converter consists of compensator for stable operations, pulse-width modulation (PWM) logic, and power switches. In order to achieve small hardware form-factor, the number of off-chip components should be kept to be minimum, which can be realized with simple and efficient frequency compensation and digital soft start-up circuits. Burst-mode operation is included for preventing the efficiency from degrading under very light load condition. The DCM DC-DC buck converter is fabricated with 0.18-um BCDMOS process. Programmable output with external resistors is typically set to be 1.8V for the input voltage between 2.8 and 5.0V. With a switching frequency of 1MHz, measured maximum efficiency is 92.6% for a load current of 100mA.

• Journal of the Korea Society of Computer and Information
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• v.26 no.2
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• pp.69-78
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• 2021

In this paper, we propose a implementation plan of the human resource pool recruitment system using private (permitted) blockchain. The term Human Resource has become commonly used and has come to recognize human resources as resources. Despite these changes, the use of human resource pools has been sluggish. Once entered, information is often not updated on a regular basis and does not provide sharing, searching, carrier management and anti-counterfeiting. In this research, in order to provide a human resource pool recruitment system that utilizes private (permitted) blockchain, we first used the blockchain network to enable sharing and searching of human resource pools, and to use keywords. Used to get results that meet certain conditions. Second, we added an institutional verification process to ensure the integrity of the input data and prepared preventive measures in the non-technical part by utilizing the structural characteristics of the blockchain to prevent counterfeiting and alteration. Third, we designed and implemented a Dapp (Decentralized application) that includes a Web UI so that each of the three groups can control the blockchain and the predefined processes and business logic.