• 한국기계가공학회지
• /
• 제20권4호
• /
• pp.49-56
• /
• 2021

This paper describes the modeling and simulation of a four-axis dedicated robot that can attach and detach a workpiece on a computer numerical control (CNC) lathe. The robot was modeled as a Scarab robot for compatibility with CNC lathes. The advantages of such a robot are that an actuator with a small capacity can be used for the robot and the degrees of freedom of the robot can be reduced to four. For the simulation of the four-axis dedicated robot, a regular kinematic equation and an inverse kinematic equation were derived. Simulations were performed with these equations from the position of the loading device to the chuck position of the lathe before machining and from the chuck of the lathe to the position of the loading device after machining. The simulation results showed that the four-axis dedicated robot could be operated accurately, and they provided the joint angle of each motor (θ1, θ2, and θ3).

• 한국재료학회지
• /
• 제18권5호
• /
• pp.272-276
• /
• 2008

In submicron MOSFET devices, maintaining the ratio between the channel length (L) and the channel depth (D) at 3 : 1 or larger is known to be critical in preventing deleterious short-channel effects. In this study, n-type SOI-MOSFETs with a channel length of $0.1\;{\mu}m$ and a Si film thickness (channel depth) of $0.033\;{\mu}m$ (L : D = 3 : 1) were virtually fabricated using a TSUPREM-4 process simulator. To form functioning transistors on the very thin Si film, a protective layer of $0.08\;{\mu}m$-thick surface oxide was deposited prior to the source/drain ion implantation so as to dampen the speed of the incoming As ions. The p-type boron doping concentration of the Si film, in which the device channel is formed, was used as the key variable in the process simulation. The finished devices were electrically tested with a Medici device simulator. The result showed that, for a given channel doping concentration of $1.9{\sim}2.5\;{\times}\;10^{18}\;cm^{-3}$, the threshold voltage was $0.5{\sim}0.7\;V$, and the subthreshold swing was $70{\sim}80\;mV/dec$. These value ranges are all fairly reasonable and should form a 'magic region' in which SOI-MOSFETs run optimally.

• 반도체디스플레이기술학회지
• /
• 제11권1호
• /
• pp.49-54
• /
• 2012

There have been plenty of difficulties because properties of Alq3 are unable to acquire in a process of manufacture of OLED. In this paper it will predict a viscosity of Alq3 through DSMC technique and suggest the way regarding a study to estimate properties of material through the computer simulation. There could generate errors of a simulation process in a vacuum deposition process since the properties of material that is used in a high-degree vacuum environment are not secured. Therefore, we would like to propose the new methods that can not only predict properties of a molecular unit but also raise an accuracy of simulation process by forecasting properties of Alq3.

• 한국정보통신학회논문지
• /
• 제5권1호
• /
• pp.157-165
• /
• 2001

집적 쇼트키 논리 게이트에서 전압 스윙을 크게 하기 위해서 백금 실리사이드 쇼트키 접합의 전기직 특성을 분석하였고, 이 접합에서 프로그램으로 특성을 시뮬레이션 하였다. 분석특성 특성을 위한 시뮬레이션 프로그램은 제조 공정용 SUPREM V와 모델링용 Matlab, 소자 구조용의 Medichi 툴이다. 시뮬레이션 특성을 위한 입력 파라미터는 소자 제작 공정의 공정 단계와 동일한 조건으로 하였다. 분석적인 전기적인 특성들은 순방향 바이어스에서 턴-온 전압, 포화 전류, 이상인자이고, 역방향 바이어스에서 항복 전압을 실제 특성과 시뮬레이션 특성 사이의 결과를 보였다. 결과로써 순방향 턴-온 전압, 역방향 항복전압, 장벽 높이는 기판의 증가된 농도의 변화에 따라 감소되었지만, 포화전류와 이상인자는 증가되었다.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1999년도 하계종합학술대회 논문집
• /
• pp.946-949
• /
• 1999

In this research we have developed a reliable, effective and feasible HEI(High-Energy Ion Implantation) process 3D-simulation tool, and then by using it we can predict and analyze the effect of HEI process on characteristics of the standard CMOS device. high-energy ion implantation above 200 keV is inevitable process to form retrograde well and buried layer to prevent leakage current, to conduct field implant for field isolation, and to perform after-gate implantation. The feasible analysis tool is a product of the HEI process modeling verified by comparison of the SIMS experiments with the simulation results. Especially, in this paper, we present the predicting capability of HEI-induced impurity and damage profiles compared with the published SIMS data in order to acquire the reliability of our results ranging from few keV to several MeV for phosphorus and boron implantation.

• 대한전기학회논문지:전기물성ㆍ응용부문C
• /
• 제52권10호
• /
• pp.451-457
• /
• 2003

The silicon wafer is stable status at room temperature, but it is weak at high temperatures which is necessary for it to be fabricated into a power semiconductor device. During thermal diffusion processing, a high temperature produces a variety thermal stress to the wafer, resulting in device failure mode which can cause unwanted oxide charge or some defect. This disrupts the silicon crystal structure and permanently degrades the electrical and physical characteristics of the wafer. In this paper, the electrical characteristics of a single oxide layer due to high temperature diffusion process, wafer resistivity and thickness of polyback was researched. The oxide quality was examined through capacitance-voltage characteristics, defect density and BMD(Bulk Micro Defect) density. It will describe the capacitance-voltage characteristics of the single oxide layer by semiconductor process and device simulation.

• Elastomers and Composites
• /
• 제53권4호
• /
• pp.226-233
• /
• 2018

Elastomers based on the thermoplastics are widely used in rubber industries. Thermoplastic elastomers have the advantages of an easy shaping process and elimination of recycling problems. Thermoplastic polyester elastomer (TPE) is used for making rubber bands in wearable devices and its applications are increasing. In this study, five wrist bands were designed and their mechanical behaviors were examined by computer simulation, using hyper elastic models, Mooney-Rivlin and Ogden models, and a linear elastic model. Simulation results were compared and discussed in terms of band design and material model.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1998년도 추계종합학술대회 논문집
• /
• pp.561-564
• /
• 1998

This paper describes a performance degradation of static type input buffer due to the device degradation in menory devices using $0.8\mu\textrm{m}$ CMOS process. experimental results shows that the degradation of MOS device affects the Trip Point shift in static type input buffer. We have performed the spice simulation and calculated the Trip Point with model parameter and measurement data so that how much the Trip Point(VLT) variate.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1998년도 추계종합학술대회 논문집
• /
• pp.537-540
• /
• 1998

A MESFET device with double $\delta-doped$ channel is designed and investigated by computer simulation. The device with optimized design parameters such as a doping ratio and a spacer thickness, shows superior performance to conventional MESFETs. The effects of the FWHM of $\delta-doped$ layers device characteristics are investigated to account for the thermal process

• 반도체디스플레이기술학회지
• /
• 제14권2호
• /
• pp.41-45
• /
• 2015

From 20nm technology node, the finFET has become standard device for ULSI's. However, the finFET process made stacking gate non-volatile memory obsolete. Some reported capacitor-less DRAM structure by utilizing the FBE. We present possible non-volatile memory device structure similar to the dual gate MOSFET. One of the gates is left floating. Since body of the finFET is only 40nm thick, control gate bias can make electron tunneling through the floating gate oxide which sits across the body. For programming, gate is biased to accumulation mode with few volts. Simulation results show that the programming electron current flows at the interface between floating gate oxide and the body. It also shows that the magnitude of the programming current can be easily controlled by the drain voltage. Injected electrons at the floating gate act similar to the body bias which changes the threshold voltage of the device.