• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.8
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• pp.8-13
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• 2009

LED BLU(Back Light Unit), based on MCPCB(Metal Core Printed Circuit Board) with anodizing oxide dielectric layer and improved thermal dissipation property, are presented. Reflecting cups were also formed on the surface of the MCPCB such that optical coupling between neighboring chips were minimized for improving the photon extraction efficiency. LED chips were directly attached on the MCPCB by using the COB (Chip On Board) scheme.

• Journal of the Korean Society for Precision Engineering
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• v.19 no.9
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• pp.151-156
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• 2002

A new position correction method using four fiducials as reference points was developed and examined. It was aimed to calibrate nonlinear deformation by numerous error sources. A correlation for correction was derived from the geometric relationship between four fiducials and chip position. Compared with three points method, it exhibited more accurate correction, especially for inner area of a quadrilateral composed of four fiducial points. Its accuracy was found to be increased as fiducials moves outwardly within a printed circuit board (PCB) and/or as they form more rectangle-like shape As for arbitrarily nonlinear deformation, this method can be applied using more than five fiducials. In this case, local-area calibration is carried out by sectioning a board area into several rectangular are as.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.10
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• pp.2935-2944
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• 2009

This paper proposes Dual DBR(Drum-Buffer-Rope) system for a small-to-medium-sized PCB(Printed Circuit Board) manufacturing line. DBR method of TOC(Theory of Constraints) is an effective system for a small-to-medium-sized company to build production scheduling system. But to apply it to PCB line, it needs more technical consideration because of multiple constraints, looping process line and complex buffer management. This paper proposes an answer of these problems using Dual DBR to build production scheduling system more successfully. And it was confirmed that lead time was reduced more than 20% applying Dual DBR system to a domestic PCB manufacturing line actually.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.4
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• pp.77-86
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• 2008

The reliability of leaded and lead-free solders of BGA type packages on a printed circuit board was investigated by employing the standard drop test and 4-point bending test. Tested solder joints were examined by optical microscopy to identify associated failure mode. Three-dimensional finite element analysis(FEM) with ANSYS Workbench v.11 was carried out to understand the mechanical behavior of solder joints under the influence of bending or drop impact. The results of numerical analysis are in good agreement with those obtained by experiments. Packages in the center of the PCB experienced higher stress than those in the perimeter of the PCB. The solder joints located in the outermost comer of the package suffered from higher stress than those located in center region. In both drop and bending impact tests, the lead-free solder showed better performances than the leaded solders. The numerical analysis results indicated that stress and strain behavior of solder joint were dependent on various effective parameters.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.2
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• pp.35-41
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• 2011

Recently, board level solder joint reliability performance of IC packages during drop impact becomes a great concern to semiconductor and electronic product manufacturers. The handheld electronic products are prone to being dropped during their useful service life because of their size and weight. The IC packages are susceptible to solder joint failures, induced by a combination of printed circuit board (PCB) bending and mechanical shock during impact. The board level drop testing is an effective method to characterize the solder joint reliability performance of miniature handheld products. In this paper, applying the JEDEC (JESD22-B111) standard present a finite element modeling of the FBGA. The simulation results revealed that maximum stress was located at the outermost solder ball in the PCB or IC package side, which consisted well with the location of crack initiation observed in the failure analysis after drop reliability tests.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1277-1281
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• 2005

FPGA has been widely used in communication system. In this paper, we made 10 layers PCB on protection of signal noise and data lose with FPGA. We analyzed about change of the data transmission speed and length according to input frequency. The length of transmission line from FPGA's output-pin to output-port on PCB board is 13cm and extended lengths for test are 30cm, 60cm and 10cm. We knew that data can be stably transmitted to 100Mbps at transmission line length of 30cm.

• Journal of the Korean Society of Safety
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• v.30 no.1
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• pp.34-39
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• 2015

The feasibility of recycling wasted printed circuit board (PCB) is investigated by preparing PCB added flame retardant composites filled with either unsaturated polyester or polyurethane. In order to improve electroconductive properties, copper powder was added into the composites, which results also in improving their antistatic properties. The prepared composite samples showed a binding between the polymer fillers observed by a scanning microscope. The sample group using unsaturated polyester is elastomeric that led to appreciable elongation and elasticity. In case of polyurethane, the tensile strength increased proportionally as increase of the amount of PCB powder. The composite materials can be utilized as antistatic composite materials, since the surface resistivity result showed increase of the electroconductive properties by adding Cu. The flammability of the samples is not satisfactory according to UL-94 vertical test. However, the flame retardant properties were improved by adding PCB power. This study, therefore, showed that it is feasible to fabricate polymer composite materials and improve the material characteristics by adding PCB powder, which can replace existing additives used for the preparation of polymer composite materials and can reduce the environment contamination by recycling the wasted PCB.

• Proceedings of the Korea Information Processing Society Conference
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• 2016.10a
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• pp.518-519
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• 2016

AOI 검사기는 SMT 공정 상에서 PCB (printed Circuit Board) 상의 부품들을 카메라로 촬영하고 촬영된 영상을 2D 혹은 3D 형태의 이미지로 재구성하고 분석하여 이상 여무를 판단하는 장비다. 검사를 하고자 하는 PCB의 크기가 카메라가 촬영할 수 있는 영역 보다 큰 경우가 대부분이기 때문에 PCB 상에 마운트 되어 있는 부품들을 모두 촬영하기 위해서는 여러 차례 나누어 촬영해야 할 필요가 있으며 이 때문에 PCB 상에 촬영해야 하는 부품들을 가능한 FOV에 많이 포함될 수 있도록 여러 FOV 영역으로 나누고 이렇게 나누어진 FOV 영역들을 최적의 경로로 이동하며 촬영할 수 있도록 하기 위한 알고리즘이 필요하다. 기존 논문들은 대부분 이 문제를 해결하기 위한 알고리즘에 대해 다루어 왔다. 일반적으로 생산이 진행되는 시점에서는 검사해야 할 PCB에 대한 정보 (PCB의 크기, 부품의 위치, 크기, 종류 등)는 이미 정해져 있기 때문에 경로 계획 최적화 수행은 PCB 정보에 변동이 없다면 한차례만 하면 된다. 하지만 검사를 할 수 있도록 Teaching 하는 단계에서는 PCB 정보가 지속적으로 변경될 수 있으며 이에 따라 최적화를 여러 차례 수행해야 할 필요성이 있다. 최적화를 위한 처리 시간은 부품의 개수, PCB 상에서의 분포정도등에 따라 증가하기 때문에 PCB 정보가 변경될 때 마다 최적화를 수행하게 되면 비효율적으로 처리 시간이 증가하게 된다. 본 논문에서는 이 문제에 대해 연구하고 해결책을 제시하였다.

• Journal of the Institute of Convergence Signal Processing
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• v.16 no.3
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• pp.90-95
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• 2015

This study presents a method to test quite small-sized and light-weighted micro-drill bits which are used to make holes in printed circuit boards(PCB). After getting images of micro-drill bits through the high resolution microscope, we developed image processing algorithms to detect fiducial points, and then measured diverse factors of the drill-bit based on these points. We also developed the window-based inspection system to automatically discriminate normal and abnormal status. For the relative comparison of its performance, the system was compared with an existing inspection system using test images. Experimental results showed that the proposed system slightly improved performance, and also classified correctly some misjudged errors which were occurred in the existing system.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.4
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• pp.101-105
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• 2019

The adhesion reliability of the epoxy molding compound (EMC) and the printed circuit board (PCB) interface is critical to the quality and lifetime of the chip package since the EMC protects PCB from the external environment during the manufacturing, storage, and shipping processes. It is necessary to measure adhesion energy accurately to ensure product reliability by optimizing the manufacturing process during the development phase. This research deals with the measurement of EMC/PCB interfacial adhesion energy of chip package that has warpage induced by the coefficient of thermal expansion (CTE) mismatch. The double cantilever beam (DCB) test was conducted to measure adhesion energy, and the spring back force of specimens with warpage was compensated to calculate adhesion energy since the DCB test requires flat substrates. The result was verified by comparing the adhesion energy of flat chip packages come from the same manufacturing process.