• 한국전자파학회논문지
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• 제14권3호
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• pp.226-232
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• 2003

본 논문에서는 파워 아일랜드(power island)의 설계지침을 연구하였다. 일반적으로 파워 아일랜드는 각 파워버스(power bus)의 구조적 공진에 의해 잡음 전달이 증가하는 단점이 있다. 따라서 본 논문에서는 잡음원의 위치를 변화시킴으로서 공진을 억제하였으며 개선된 잡음 특성을 위해서 EGI(Elevated Ground Island)를 제안하였다. 해석결과, 잡음원의 위치에 따라 파워 버스의 공진을 최소로 감소시켰으며, EGI를 이용하여 공진에 의해 발생되는 잡음 전달을 11 $\Omega$까지 감소시켰다.

• 전기학회논문지
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• 제60권1호
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• pp.20-25
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• 2011

This paper analyzed the application of Superconducting Fault Current Limiter (SFCL) on 22.9 [kV] bus tie in a power distribution system. Commonly, the parallel operations of power main transformers offer a lot of merits. However, when a fault occurs in the parallel operation of power main transformer, the fault currents might exceed the interruption capacity of existing protective devices. To resolve this problem, thus, the SFCL has been studied as the fascinating device. In case that, Particularly, the SFCL could be installed to parallel operation of various power main transformers in power distribution system of the Korea Electric Power Corporation (KEPCO) on 22.9 [kV] bus tie, the effect of the resistance of SFCL could reduce the increased fault currents and meet the interruption capacity of existing protective devices by them. Therefore, we analyzed the effect of application and proposed the proper impedance of the R-type SFCL on 22.9 [kV] bus tie in a power distribution system using PSCAD/EMTDC.

• 제어로봇시스템학회논문지
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• 제6권1호
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• pp.42-49
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• 2000

This paper presents the application of a FARMA controller to stabilization of nonlinear Two-Generator Five-Bus power Systems. The control rules and the membership functions of the FARMA controller are generated automatically without using any plant model high complexity and severe nonlinearity of power systems are introduced and two-Machine Five -Bus Power system stabilization problem is formulated. The simulation results demonstrate the effectiveness and application possibility of the FARMA controller to the control problem of high order and nonlinear plants.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권2호
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• pp.75-79
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• 2009

A system-on-a-chip communication architecture has a significant impact on the performance and power consumption of modern multi-processors system-on-chips (MPSoCs). However, customization of such architecture for a specific application requires the exploration of a large design space. Thus, system designers need tools to rapidly explore and evaluate communication architectures. In this paper we present the method for application-specific low-power bus architecture synthesis at system-level. Our paper has two contributions. First, we build a bus power model of AMBA AXI bus communication architecture. Second, we incorporate this power model into a low-power architecture exploration algorithm that enables system designers to rapidly explore the target bus architecture. The proposed exploration algorithm reduces power consumption by 20.1% compared to a maximally connected reduced matrix, and the area is also reduced by 20.2% compared to the maximally connected reduced matrix.

• Transactions on Electrical and Electronic Materials
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• 제17권1호
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• pp.1-6
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• 2016

Ensuring the secure operation of power systems has become an important and critical matter during the present time, along with the development of large, complex and load-increasing systems. Security constraints such as the thermal limits of transmission lines and bus-voltage limits must be satisfied under all of a system’s operational conditions. An alternative solution to improve the security of a power system is the employment of Flexible Alternating-Current Transmission Systems (FACTS). FACTS devices can reduce the flows of heavily loaded lines, maintain the bus voltages at desired levels, and improve the stability of a power network. The Unified Power Flow Controller (UPFC) is a versatile FACTS device that can independently or simultaneously control the active power, the reactive power and the bus voltage; however, to achieve such functionality, it is very important to determine the optimal location of the UPFC device, with the appropriate parameter setting, in the power system. In this paper, a genetic algorithm (GA) method is applied to determine the optimal location of the UPFC device in a network for the enhancement of the power-system loadability and the minimization of the active power loss in the transmission line. To verify our approach, simulations were performed on the IEEE 14 Bus, 30 Bus, and 57 Bus test systems. The proposed work was implemented in the MATLAB platform.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1994년도 하계학술대회 논문집 A
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• pp.348-350
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• 1994

In this paper, bi-directional buck-boost DC-DC converter for bus regulation system is presented. This converter which has one buck and one boost topology achieves bi-directional power flow using a common power inductor and alternative power switches. By connecting the battery to bus line, it can be regulated to bus voltage and charged the battery alternatively. And as an application, a mode controller is adopted to the converter.

• 한국전자파학회논문지
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• 제17권2호
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• pp.148-151
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• 2006

PCB에서의 전자파 간섭원으로 DC power-bus의 공진이 자주 지목된다. 이것은 결국, 전도성 또는 전파 방사의 형태로, 하나 또는 인접한 시스템에서 디지털 SI를 저하시키게 된다. 따라서 PCB의 방사 문제를 파악하는 것은 중요하므로, 본 논문은 DC power-bus 공진 모드에 대한 방사를 면밀히 살펴본다. 엄밀한 주파수 영역 해석법을 이용하여 임피던스와 방사 전계를 구하고, 이는 물리와 전자파 해석 모의시험에 의해 타당성이 검토된다.

• 한국정보과학회논문지:시스템및이론
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• 제29권12호
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• pp.680-686
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• 2002

딥 서브 마이크론 (DSM: deep-submicron) 설계에서는 버스에서 선들 간의 커플링 효과는 크로스톡 지연, 노이즈, 전력 소모와 같은 심각한 문제를 야기 시킨다. 버스 인코딩에 대한 대부분의 이전 연구들은 버스에서의 전력 소모를 최소화하거나 크로스톡 지연을 최소화하는데 초점을 맞추고 있지만 모두를 고려한 방법은 보이지 않는다. 이 논문에서, 우리는 버스에서의 전력 소모 최소화와 크로스톡 지연 방지를 동시에 고려한 새로운 버스 인코딩 알고리즘을 제안하였다. 우리는 이 문제를 공식화하여, 자체 천이와 상호 천이의 가중 합 문제를 풂으로써 해결하였다. 여러 벤치마크 설계를 이용한 실험으로부터 제안한 인코딩 방법을 이용할 경우, 크로스톡 지연을 완전히 제거할 뿐 아니라 이전의 방법들을 사용한 것 보다 최소 15% 이상 적은 전력을 소모하였음을 보았다.

• Journal of electromagnetic engineering and science
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• 제6권4호
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• pp.197-202
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• 2006

This paper presents a study on the differential signaling for the rectangular power-bus structure. The full-wave modal analysis method analyzes how the differential-signaling can lower the power-bus resonance noise levels. The methodology is validated by the use of the FDTD method and reference measurements.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2005년도 종합학술발표회 논문집 Vol.15 No.1
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• pp.429-432
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• 2005

This paper investigates how the PCB power-bus structure's characteristics are influenced by the loading of decoupling capacitors that are placed close to vias, on purpose or not. It is worthwhile to see the correlated effects of the aforementioned lumped elements in that when they inevitably share one DC power-bus they will result in positive or negative changes in the PCB EMC design. The EM fields and impedance profiles are rigously calculated on the PCB power-bus cases loaded with the above components and their effects will be given to bring better PCB EMC countermeasures.