• Title/Summary/Keyword: Power scheduling

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Profit-based Thermal Unit Maintenance Scheduling under Price Volatility by Reactive Tabu Search

  • Sugimoto Junjiro;Yokoyama Ryuichi
    • KIEE International Transactions on Power Engineering
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    • v.5A no.4
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    • pp.331-338
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    • 2005
  • In this paper, an improved maintenance scheduling approach suitable for the competitive environment is proposed by taking account of profits and costs of generation companies and the formulated combinatorial optimization problem is solved by using Reactive Tabu search (RTS). In competitive power markets, electricity prices are determined by the balance between demand and supply through electric power exchanges or by bilateral contracts. Therefore, in decision makings, it is essential for system operation planners and market participants to take the volatility of electricity price into consideration. In the proposed maintenance scheduling approach, firstly, electricity prices over the targeted period are forecasted based on Artificial Neural Network (ANN) and also a newly proposed aggregated bidding curve. Secondary, the maintenance scheduling is formulated as a combinatorial optimization problem with a novel objective function by which the most profitable maintenance schedule would be attained. As an objective function, Opportunity Loss by Maintenance (OLM) is adopted to maximize the profit of generation companies (GENCOS). Thirdly, the combinatorial optimization maintenance scheduling problem is solved by using Reactive Tabu Search in the light of the objective functions and forecasted electricity prices. Finally, the proposed maintenance scheduling is applied to a practical test power system to verify the advantages and practicability of the proposed method.

Vertex Coloring based Slot Reuse Scheduling for Power Line Communications

  • Yoon, Sung-Guk
    • Journal of Electrical Engineering and Technology
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    • v.10 no.5
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    • pp.2135-2141
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    • 2015
  • Power line communication (PLC) is one of the major communication technologies in smart grid since it combines good communication capability with easy and simple deployment. As a power network can be modeled as a graph, we propose a vertex coloring based slot reuse scheduling in the time division multiple access (TDMA) period for PLCs. Our objective is to minimize the number of assigned time slots, while satisfying the quality of service (QoS) requirement of each station. Since the scheduling problem is NP-hard, we propose an efficient heuristic scheduling, which consists of repeated vertex coloring and slot reuse improvement algorithms. The simulation results confirm that the proposed algorithm significantly reduces the total number of time slots.

An Energy Efficient Algorithm Based on Clustering Formulation and Scheduling for Proportional Fairness in Wireless Sensor Networks

  • Cheng, Yongbo;You, Xing;Fu, Pengcheng;Wang, Zemei
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.10 no.2
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    • pp.559-573
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    • 2016
  • In this paper, we investigate the problem of achieving proportional fairness in hierarchical wireless sensor networks. Combining clustering formulation and scheduling, we maximize total bandwidth utility for proportional fairness while controlling the power consumption to a minimum value. This problem is decomposed into two sub-problems and solved in two stages, which are Clustering Formulation Stage and Scheduling Stage, respectively. The above algorithm, called CSPF_PC, runs in a network formulation sequence. In the Clustering Formulation Stage, we let the sensor nodes join to the cluster head nodes by adjusting transmit power in a greedy strategy; in the Scheduling Stage, the proportional fairness is achieved by scheduling the time-slot resource. Simulation results verify the superior performance of our algorithm over the compared algorithms on fairness index.

A Low Power Resource Allocation and Scheduling Algorithm for High Level Synthesis (상위 레벨 합성을 위한 저 전력 스케줄링 및 자원할당 알고리즘)

  • Sin, Mu-Kyoung;Lin, Chi-Ho
    • The KIPS Transactions:PartA
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    • v.8A no.3
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    • pp.279-286
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    • 2001
  • This paper proposes a low power resource allocation and scheduling algorithm that minimized power consumption such as DSP circuit in high-level synthesis process. In this paper, we have used list-scheduling method for low power design in scheduling step. Also, it increase possibility to reuse input through resource sharing when assign resource. After scheduling, the resources allocation uses the power function in consideration of the result of calculating average hamming distances and switching activity between two input. First, it obtain switching activity about input value after calculate average hamming distances between two operator and find power value make use of bit pattern of the input value. Resource allocation process assign operator to minimize average hamming distance and power dissipation on all occasions which is allocated at each control step according to increase control step. As comparing the existed method, the execution time becomes fast according to number of operator and be most numberous control step. And in case of power that consume, there is decrease effect from 6% to 8% to be small.

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Evaluation and Analysis of Scheduling Algorithms for Peak Power Reduction (전력 피크 감소를 위한 스케줄링 알고리즘의 성능 평가 및 분석)

  • Sung, Minyoung
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.16 no.4
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    • pp.2777-2783
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    • 2015
  • Peak power reduction is becoming increasingly important not only for grid operators but also for residential users. The scheduling of electric loads tries to reduce the power peak by splitting the power-on period of an electric device into multiple smaller ones and by interleaving the on-periods of every device in a holistic way. This paper analyzes the performance of EDF, LSF, TCBM, and lazy scheduling algorithms and proposes the enhancement schemes. For analysis, we have implemented the scheduling policies in a simulation environment for distributed control systems. Through extensive experiments using real power traces, we discuss their performance characteristics in terms of power deviation, switch count, and temperature violation ratio. To prevent excessive switching, we propose to employ the concept of limited preemptibility and evaluate its effect on performance. It is found that the best performance is achieved when the scheduler capacity is dynamically adjusted to the actual power demand. The experiment results show that, by load scheduling, the probability of having a power deviation greater than 150W is reduced from 21.5% down to 3.2%.

A Minimal Power Scheduling Algorithm for Low Power Circuit Design

  • Lin, Chi-Ho
    • Proceedings of the IEEK Conference
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    • 2002.07a
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    • pp.212-215
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    • 2002
  • In this paper, we present an intermediate representation CDFG(Control Data Flow Graph) and an efficient scheduling technique for low power circuit design. The proposed CDFG represents control flow, data dependency and such constraints as resource constraints and timing constraints. In the scheduling technique, the constraints are substituted by subgraphs, and then the number of subgraphs is minimized by using the inclusion and overlap relation efficiently. Also, iterative rescheduling process are performed in a minimum bound estimation, starting with the as soon as possible as scheduling result, so as to reduce the power consumption in low power design. The effectiveness of the proposed algorithm has been proven by the experiment with the benchmark examples.

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Clock Scheduling and Cell Library Information Utilization for Power Supply Noise Reduction

  • Kim, Yoo-Seong;Han, Sang-Woo;Kim, Ju-Ho
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.9 no.1
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    • pp.29-36
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    • 2009
  • Power supply noise is fundamentally caused by large current peaks. Since large current peaks are induced by simultaneous switching of many circuit elements, power supply noise can be minimized by deliberate clock scheduling which utilizes nonzero clock skew. In this paper, nonzero skew clock scheduling is used to avoid the large peak current and consequently reduce power supply noise. While previous approaches require extra characterization efforts to acquire current waveform of a circuit, we approximate it only with existing cell library information to be easily adapted to conventional design flow. A simulated annealing based algorithm is performed, and the peak current values are estimated for feasible clock schedules found by the algorithm. The clock schedule with the minimum peak current is selected for a solution. Experimental results on ISCAS89 benchmark circuits show that the proposed method can effectively reduce the peak current.

Reducing Power Consumption of a Scheduling for Reuse Module Selection under the Time Constraint (시간 제약 조건 하에서의 모듈 선택 재사용을 위한 전력 감소 스케줄링)

  • 최지영;김희석
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.3A
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    • pp.318-323
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    • 2004
  • In this paper, we present a reducing power consumption of a scheduling for reuse module selection under the time constraint. Traditional high-level synthesis do not allow reuse of complex, realistic datapath component during the task of scheduling. On the other hand, the proposed scheduling of reducing power consumption is able to approach a productivity of the design the low power to reuse which given a library of user-defined datapath component and to share of resource sharing on the switching activity in a shared resource. Also, we are obtainable the optimal the scheduling result in experimental results of our approach various HLS benchmark environment using chaining and multi-cycling in the scheduling techniques.

Constrained Multi-Area Dispatch Scheduling Algorithm with Regionally Distributed Optimal Power Flow Using Alternating Direction Method (ADM 기반 분산처리 최적조류계산을 이용한 다지역 제약급전계획 알고리즘)

  • Chung, Koo-Hyung;Kim, Bal-Ho;Lee, Jong-Joo;Kim, Hak-Man
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.59 no.3
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    • pp.245-252
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    • 2010
  • This paper proposes a constrained multi-area dispatch scheduling algorithm applicable to interconnected power system operations. The dispatch scheduling formulated as an MIP problem can be efficiently computed by GBD algorithm. GBD guarantees adequate computation speed and solution convergence by reducing the dimension of the dispatch scheduling problem. In addition, the regional decomposition technique based on ADM is introduced to obtain efficient inter-temporal OPF solution. It can find the most economic dispatch schedule incorporating power transactions without each regional utility's private information open.

An Improved Task Scheduling Algorithm for Efficient Dynamic Power Management in Real-Time Systems (실시간 시스템에서 효율적인 동적 전력 관리를 위한 태스크 스케줄링 알고리듬에 관한 연구)

  • Lee Won-Gyu;Hwang Sun-Young
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.4A
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    • pp.393-401
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    • 2006
  • Energy consumption is an important design parameter for battery-operated embedded systems. Dynamic power management is one of the most well-known low-power design techniques. This paper proposes an online realtime scheduling algorithm, which we call energy-aware realtime scheduling using slack stealing (EARSS). The proposed algorithm gives the highest priority to the task with the largest degree of device overlap when the slack time exists. Scheduling result enables an efficient power management by reducing the number of state transitions. Experimental results show that the proposed algorithm can save the energy by 23% on average compared to the DPM-enabled system scheduled by the EDF algorithm.