Reducing Power Consumption of a Scheduling for Reuse Module Selection under the Time Constraint |
최지영
(제천기능대학 정보통신설비과)
김희석 (청주대학교 전자공학과) |
1 |
Low-Power CMOS Digital Design
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DOI ScienceOn |
2 |
Behavioral to Structural Translation in a Bit-Serial Silicon Compiler
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3 |
Estimation of Average Switching Activity in Combination and Sequential Circuits
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4 |
Power-Profiler: Optimizing ASICs Power Consumption at the Behavioral Level
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5 |
Minimizing Power Consumption in Digital CMOS Circuits
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DOI ScienceOn |
6 |
Register Allocation and Binding for Low Power
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7 |
Power Estimation of High-Level Synthesis
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8 |
HYPER-LP: A System fo Power Minimization Using Architecture Transformation
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