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Reducing Power Consumption of a Scheduling for Reuse Module Selection under the Time Constraint  

최지영 (제천기능대학 정보통신설비과)
김희석 (청주대학교 전자공학과)
Abstract
In this paper, we present a reducing power consumption of a scheduling for reuse module selection under the time constraint. Traditional high-level synthesis do not allow reuse of complex, realistic datapath component during the task of scheduling. On the other hand, the proposed scheduling of reducing power consumption is able to approach a productivity of the design the low power to reuse which given a library of user-defined datapath component and to share of resource sharing on the switching activity in a shared resource. Also, we are obtainable the optimal the scheduling result in experimental results of our approach various HLS benchmark environment using chaining and multi-cycling in the scheduling techniques.
Keywords
시간 제약;모듈선택;재사용;전력감소;스케줄링;
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  • Reference
1 Low-Power CMOS Digital Design /
[ A.Chandrakasan(et al.) ] / J. Solid-Stat Circuits   DOI   ScienceOn
2 Behavioral to Structural Translation in a Bit-Serial Silicon Compiler /
[ R.Hartley ] / IEEE Trans. CAD
3 Estimation of Average Switching Activity in Combination and Sequential Circuits /
[ A.Ghosh ] / Proc. 29th DAC
4 Power-Profiler: Optimizing ASICs Power Consumption at the Behavioral Level /
[ R.Martin ] / Proc. 32nd DAC
5 Minimizing Power Consumption in Digital CMOS Circuits /
[ A.Chandrakasan;R.Brodersen ] / IEEE Proceedings   DOI   ScienceOn
6 Register Allocation and Binding for Low Power /
[ J.Chang ] / Proc. 32nd DAC
7 Power Estimation of High-Level Synthesis /
[ P.Landman ] / Proc. European DAC
8 HYPER-LP: A System fo Power Minimization Using Architecture Transformation /
[ A.Chandarksan(et al.) ] / Proc. ICCAD