• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.159-168
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• 2012

In this paper, a W-band single-chip receiver MMIC for FMCW(Frequency-modulated continuous-wave) radar is presented using $0.15{\mu}m$ GaAs pHEMT technology. The receiver MMIC consists of a 4-stage low noise amplifier(LNA), a down-converting mixer and a 3-stage LO buffer amplifier. The LNA is designed to exhibit a low noise figure and high linearity. A resistive mixer is adopted as a down-converting mixer in order to obtain high linearity and low noise performance at low IF. An additional LO buffer amplifier is also demonstrated to reduce the required LO power of the W-band mixer. The fabricated W-band single-chip receiver MMIC shows an excellent performance such as a conversion gain of 6.2 dB, a noise figure of 5.0 dB and input 1-dB compression point($P_{1dB,in}$) of -12.8 dBm, at the RF frequency of $f_0$ GHz, LO input power of -1 dBm and IF frequency of 100 MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.65-72
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• 2008

This paper proposes a new dual-loop digital PLL(DPLL) using seamless frequency tracking methods. The dual-loop construction, which is composed of the coarse and fine loop for fast locking time and a switching noise suppression, is used successive approximation register technique and TDC. The proposed DPLL in order to compensate the quality of jitter which follows long-term of input frequency is newly added cord conversion frequency tracking method. Also, this DPLL has VCO circuitry consisting of digitally controlled V-I converter and current-control oscillator (CCO) for robust jitter characteristics and wide lock range. The chip is fabricated with Dongbu HiTek $0.18-{\mu}m$ CMOS technology. Its operation range has the wide operation range of 0.4-2GHz and the area of $0.18mm^2$. It shows the peak-to-peak period jitter of 2 psec under no power noise and the power dissipation of 18mW at 2GHz through HSPICE simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.1-11
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• 2008

This work proposes a 15b 50MS/s CMOS pipeline ADC based on digital code-error calibration. The proposed ADC adopts a four-stage pipeline architecture to minimize power consumption and die area and employs a digital calibration technique in the front-end stage MDAC without any modification of critical analog circuits. The front-end MDAC code errors due to device mismatch are measured by un-calibrated back-end three stages and stored in memory. During normal conversion, the stored code errors are recalled for code-error calibration in the digital domain. The signal insensitive 3-D fully symmetric layout technique in three MDACs is employed to achieve a high matching accuracy and to measure the mismatch error of the front-end stage more exactly. The prototype ADC in a 0.18um CMOS process demonstrates a measured DNL and INL within 0.78LSB and 3.28LSB. The ADC, with an active die area of $4.2mm^2$, shows a maximum SNDR and SFDR of 67.2dB and 79.5dB, respectively, and a power consumption of 225mW at 2.5V and 50MS/s.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.4
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• pp.596-601
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• 2020

Silicon carbide is considered a potentially useful material for high-temperature electronic devices because of its large band gap energy and p-type or n-type conduction that can be controlled by impurity doping. Accordingly, the thermoelectric properties of -SiC powder prepared by refined diatomite were investigated for high value-added applications of natural diatomite. -SiC powder was synthesized by a carbothermal reduction of the SiO₂ in refined diatomite using carbon black. An acid-treatment process was then performed to eliminate the remaining impurities (Fe, Ca, etc.). n-Type semiconductors were fabricated by sintering the pressed powder at 2000℃ for 1~5h in an N2 atmosphere. The electrical conductivity increased with increasing sintering time, which might be due to an increase in carrier concentration and improvement in grain-to-grain connectivity. The carrier compensation effect caused by the remaining acceptor impurities (Al, etc.) in the obtained -SiC had a deleterious influence on the electrical conductivity. The absolute value of the Seebeck coefficient increased with increasing sintering time, which might be due to a decrease in the stacking fault density accompanied by grain or crystallite growth. On the other hand, the power factor, which reflects the thermoelectric conversion efficiency of the present work, was slightly lower than that of the porous SiC semiconductors fabricated by conventional high-purity -SiC powder, it can be stated that the thermoelectric properties could be improved further by precise control of an acid-treatment process.

• Journal of the Korea Computer Industry Society
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• v.8 no.2
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• pp.107-112
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• 2007

Laser wave length can have evaporation effect by absorption because outer skin or tissue of focus is consisted of water almost though absorption of water occurs more than 90% almost in formation thickness of very thin floor. Can operate outer skin, steam by floor and correct incision of formation is available. Suture surgical operation is available to vein or lymph system and surgical operation region can dry and see as eye and radish bleeding surgical operation is available. Specially, stability of tube both end output about pulse by weight very, this research can cause various curative effect because can reduce bulk and control easily current wave style of medical laser using electric power conversion device of high frequency way. If introduce ZVS (Zero Voltage Switching) or ZVZCS (Zero Voltage and Zero Current Switching), is more profitable because can reduce switching damage. Because electric power department of proposed medical laser can do stable soft-switching in wide subordinate extent introducing ZVZCS technique by the first help and control department composes microcontroller, output current waveform user have free form make Result that experiment because design and manufacture, brought result that improve of 20% than existing equipment, and will be bought to get into superior result if supplement as systematic late.

• Journal of Energy Engineering
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• v.25 no.3
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• pp.27-33
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• 2016

The heat recovery system that was applied in this study, is the energy-saving type that can produce the maximum cooling capacity less power in use. In order to have a more precise control function the temperature and humidity of the constant temperature and humidity machine, control algorithm is applied to designed a fuzzy PID controller, and the outside air compensation device (air-cooled) demonstrated excellent ability to dehumidify the moisture, $-20^{\circ}C$ in winter. High efficiency and the low-noise type sirocco fan operate quitely and designed to fit the bottom-up and top-down in accordance with the characteristics of equipment. as a result of experiment data, the conversion efficiency is 95% or more, power recovery time is within 5sec, stop delay time is within 30sec, pump down time is 10sec, pump delay time is 5sec, heating delay time is 5sec, temperature deviation is ${\pm}2^{\circ}C$ (cooling deviation: $2^{\circ}C$, Heating deviation : $2^{\circ}C$), humidity deviation is a ${\pm}5%$ (humidification deviation 3.0%, dehumidification deviation 3.0%). Recently, ubiquitous technology is important. so, the constant temperature and humidity machine designed to be able to remotely control to via the mobile phone, and more scalable to support MMI software and automatic interface. Further, the life of the parts and equipment is extended by the failure.

• Journal of the Economic Geographical Society of Korea
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• v.11 no.2
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• pp.216-232
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• 2008

This paper aim to review the extent of Park Je-Ga's geographical interest and knowledge and where he intended to make good use of them through Bukhakui(北學議). In particular, it was classified and interpreted as the contents related to agricultural, industrial and commercial geography focusing on the contents of the economic geography. As for the contents related to agricultural geography, it suggests minutely and precisely the necessity and concrete methodology for farmland, seeding, fertilization, breeding of cattle, sericulture and fruits. As for the contents related to industrial geography, it lays emphasis on the pursuit of the modernization of ours by means of accepting high-tech, industrial engineering and knowledge from Western scholars who were staying in Beijing. As for the contents related to commercial geography, it puts emphasis on the conversion of idle labor capacity of the nobility to practical production capacity, the pursuit of economic vitalization by opening land transportation through wheels and the trade by sea with neighboring countries such as Qing, Japan, Ryukyu, Vietnam and so on. It can be known through this study that Park Je-Ga was a realist who made an effort to raise the economic power of the region and the country with using his endeavor of economic geographical interest and knowledge. His economic geographical interest and knowledge were connected directly with practical use. If his economic geographical knowledge and way of thinking had been accepted successfully at that time, the economic power in the latter half of the Joseon dynasty could have leaped to a considerable degree.

• Clean Technology
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• v.23 no.2
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• pp.121-132
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• 2017

The increase of greenhouse gases and the concern of global warming instigate the development and spread of renewable energy and hydrogen is considered one of the clean energy sources. Hydrogen is one of the most elements in the earth and exist in the form of fossil fuel, biomass and water. In order to use hydrogen for a clean energy source, the hydrogen production method should be eco-friendly and economic as well. There are two different hydrogen production methods: conventional thermal method using fossil fuel and renewable method using biomass and water. Steam reforming, autothermal reforming, partial oxidation, and gasification (using solid fuel) have been considered for hydrogen production from fossil fuel. When using fossil fuel, carbon dioxide should be separated from hydrogen and captured to be accepted as a clean energy. The amount of hydrogen from biomass is insignificant. In order to occupy noticeable portion in hydrogen industries, biomass conversion, especially, biological method should be sufficiently improved in a process efficiency and a microorganism cultivation. Electrolysis is a mature technology and hydrogen from water is considered the most eco-friendly method in terms of clean energy when the electric power is from renewable sources such as photovoltaic cell, solar heat, and wind power etc.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.54-63
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• 2006

This work proposes a 14b 100MS/s 0.18um CMOS ADC with optimized resolution, conversion speed, die area, and power dissipation to obtain the performance required in the fourth-generation mobile communication systems. The 3-stage pipeline ADC, whose optimized architecture is analyzed and verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3-D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b flash ADC based on open-loop offset sampling and interpolation to obtain 6b accuracy and small chip area at 100MS/s. The prototype ADC implemented in a 0.18um CMOS process shows the measured DNL and INL of maximum 1.03LSB and 5.47LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 59dB and 72dB, respectively, and a power consumption of 145mW at 100MS/s and 1.8V. The occupied active die area is $3.4mm^2$.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.236-244
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• 2003

In this paper, RF and IF circuits for mobile terminals which have usually been implemented using expensive BiCMOS processes are designed using CMOS circuits, and a Tx CMOS RF/IF single chip for PCS applications is designed. The designed circuit consists of an IF block including an IF PLL frequency synthesizer, an IF mixer, and a VGA and an RF block including a SSB RF mixer and a driver amplifier, and performs all transmit signal processing functions required between digital baseband and the power amplifier. The phase noise level of the designed IF PLL frequency synthesizer is -114dBc/Hz@100kHz and the lock time is less than $300{\mu}s$. It consumes 5.3mA from a 3V power supply. The conversion gain and OIP3 of the IF mixer block are 3.6dB and -11.3dBm. It consumes 5.3mA. The 3dB frequencies of the VGA are greater than 250MHz for all gain settings. The designed VGA consumes 10mA. The designed RF block exhibits a gain of 14.93dB and an OIP3 of 6.97dBm. The image and carrier suppressions are 35dBc and 31dBc, respectively. It consumes 63.4mA. The designed circuits are under fabrication using a $0.35{\mu}m$ CMOS process. The designed entire chip consumes 84mA from a 3V supply, and its area is $1.6㎜{\times}3.5㎜$.