• Journal of the Korea Society of Computer and Information
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• v.16 no.6
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• pp.11-20
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• 2011

In this paper, we propose an optimal scheduling scheme that minimizes the energy consumption of a real-time video task on the multi-core platform supporting dynamic voltage and frequency scaling. Exploiting parallel execution on multiple cores for less energy consumption, the propose scheme allocates an appropriate number of cores to the task execution, turns off the power of unused cores, and assigns the lowest clock frequency meeting the deadline. Our experiments show that the proposed scheme saves a significant amount of energy, up to 67% and 89% of energy consumed by two previous methods that execute the task on a single core and on all cores respectively.

• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.68-77
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• 2018

Regarding demand response (DR) by residential users (R-users), the users try to reduce electricity costs by adjusting their power consumption in response to the time-varying price. However, their power consumption may be affected not only by the price, but also by user convenience for using appliances. This paper proposes a methodology for appliance scheduling (AS) that considers the user convenience based on historical data. The usage pattern for appliances is first modeled applying the copula function or clustering method to evaluate user convenience. As the modeling results, the comfort distribution or representative scenarios are obtained, and then used to formulate a discomfort index (DI) to assess the degree of the user convenience. An AS optimization problem is formulated in terms of cost and DI. In the case study, various AS tasks are performed depending on the weights for cost and DI. The results show that user convenience has significant impacts on AS. The proposed methodology can contribute to induce more DR participation from R-users by reflecting properly user convenience to AS problem.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.9A
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• pp.1091-1100
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• 2004

In this paper, we present a reducing power conswnption of a scheduling for module selection under the time constraint. The proposed low power scheduling executes FDS_LP considering low power to exist the FDS scheduling by inputted the behavioral language. The proposed FDS_LP perfonns lower power consumption with dynamic power which is minimized the switching activity, based on force conception In the time step of module selection, an optimal RT(Register Transfer) library is composed by exploration of the parameters such as power, area, and delay. To find optimal parameters of RT library, an optimal module selection algorithm using Branch and Bound algorithm is also proposed. In the comparison and experimental results, The proposed FDS_LP algorithm reduce maximum power saving up to 23.9% comparing to previous FDS algorithm.

• Journal of Digital Contents Society
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• v.9 no.3
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• pp.471-481
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• 2008

Test scheduling considering power dissipation is an effective technique to reduce the testing time of complex SoCs and to enhance fault coverage under limitation of allowed maximum power dissipation. In this paper, a modeling technique of test resources and a test scheduling algorithm for efficient test procedures are proposed and confirmed. For test resources modeling, two methods are described. One is to use the maximum point and next maximum point of power dissipation in test resources, the other one is to model test resources by partitioning of them. A novel heuristic test scheduling algorithm, using the extended-tree-growing-graph for generation of maximum embedded cores usable simultaneously by using relations between test resources and cores and power-dissipation-changing-graph for power optimization, is presented and compared with conventional algorithms to verify its efficiency.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.438-440
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• 2004

Energy consumption has become an increasingly important consideration in designing real-time embedded systems. In this paper, we propose a voltage scaling method to reduce energy consumption in fixed priority real-time systems using variable voltage processors. The Hyperperiod of tasks is divided into dimains. The most suitable voltage of each domain is determined off-line and stored in a table. During task execution, the voltage of processor is adjusted according to the information of the table. A simulation result shows that the proposed method can reduce 80% of power consumption in comparison to no power management. The difference to the optimal EDF based method is only 5%.

• ETRI Journal
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• v.38 no.5
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• pp.885-895
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• 2016

The lowest power mode (passive-standby mode) was proposed for reducing the power consumption of set-top boxes in a standby state when not receiving content. However, low-power set-top boxes equipped with the lowest power mode have been rarely commercialized because of their low-quality user experience. In the lowest power mode, they deactivates almost all of operational modules and processes, and thus require dozens of seconds for activation latency (that is, the latency for activating all modules of the set-top boxes in a standby state). They are not even updated in a standby state because they deactivate their network interfaces in a standby state. This paper proposes an adaptive standby mode scheduling method for improving the user experience of such boxes. Set-top boxes using the proposed method can analyze the activation pattern and find the frequently used time period (that is, when the set-top boxes are frequently activated). They prepare for their activation during this frequently used time period, thereby reducing the activation latency and enabling their update in a standby state.

• Proceedings of the Korean Information Science Society Conference
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• 2002.04a
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• pp.676-678
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• 2002

In this work, we present the novel scheduling algorithm of the multimedia data retrieval for the mobile disk drive. Our algorithm is focused on minimizing the power consumption involved in data retrieval from the local disk drive. The prime commodity in mobile devices is the electricity. Strict restriction on power consumption requirement of the mobile device put unique demand in designing of its hardware and software components. State of the art disk based storage subsystem becomes small enough to be embedded in handhold devices. It delivers abundant storage capacity and portability. However, it is never be trivial to integrate small hard disk or optical disk drive in handhold devices due to its excessive power consumption. Our algorithm ARM in this article generates the optimal schedule of retrieving data blocks from the mobile disk drive while guaranteeing continuous playback of multimedia data.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2001.06a
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• pp.73-76
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• 2001

High-level synthesis generates a structural design that implements the given behavior and satisfies design constraints for area, performance, power consumption, packaging, testing and other criteria. Thus, high-level synthesis generates that register-transfer(RT) level structure from algorithm level description. High-level synthesis consist of compiling, partitioning, scheduling. In this paper, we proposed the efficient scheduling algorithm that find the number of the functional unit and scheduling into the minimum control step with silicon area resource constrained.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.5
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• pp.1-17
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• 1997

With the increasing performance and density of VLSI scircuits as well as the popularity of portable devices such as personal digital assitance, power consumption has emerged as an important issue in the design of electronic systems. Low power design techniqeus have been pursued at all design levels. However, it is more effective to attempt to reduce power dissipation at higher levels of abstraction which allow wider view. In this paper, we propose a simultaneous scheduling and binding scheme which increases the correlation between cosecutive inputs to an operation so that the switched capacitance of execution units is reduced in datapath-dominated circuits. The proposed method is implemented and integrated into the scheduling and assignment part of HYPER synthesis environment. Compared with original HYPER synthesis system, average power saving of 23.0% in execution units and 14.2% in the whole circuits, ar eobtained for a set of benchmark examples.

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.6
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• pp.177-184
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• 2015

This paper proposes a minimum-power scheduling scheme of real-time parallel tasks while meeting deadlines of the real-time tasks on DVFS-enabled multicore processors. The proposed scheme first finds a floating number of processing cores to each task so that the computation load of all processing cores would be equalized. Next the scheme translates the found floating number of cores into a natural number of cores while maintaining the computation load of all cores unchanged, and allocates the translated natural number of cores to the execution of each task. The scheme is designed to minimize the power consumption of the frequency-sharing multicore processor operating with the same processing speed at an instant time. Evaluation shows that the scheme saves up to 38% power consumption of the previous method.