1 |
R. Hartley, 'Behavioral to Structural Translation in a Bit-Serial Silicon Compiler,' IEEE Trans. CAD, vol. 7. no. 8, Aug. 1988, pp.877-886
|
2 |
A. Dasgupta and R. Karri, 'Simultaneous scheduling and binding for low power minimization during microarchitecture synthesis,' in Proc. Int. symp. Low-Power design, Apr.1995, pp.69-74
|
3 |
H.Singh and D. D. Gajski, 'A Design Methodology for Behavioral Level Power Exploradon: Implementation and Experiments',Technical Report 397-28, University ofCalifornia, lrvine, 1997
|
4 |
J.-M. Chang and M. Pedram,' Energy minimization using multiple supply voltage',IEE E Trans. VLSI Syst., vol. 5, Dec. 1997
|
5 |
P. Landman, Power Estimation of High-Level Synthesis', in Proc. European DAC, Feb. 1993, pp.361-366
|
6 |
A. chandraksan and R. Brodersen, 'Minimizing power consumption in digital CMOS circuit." in Proc. IEEE, vol.83, Apr. 1995, pp.498-523
DOI
ScienceOn
|
7 |
A. Chandarksan et aI., 'HYPER-LP: A System fo Power Minimization Using Architecture Transformation,' in Proc. ICCAD, Nov. 1992, pp.300-303
|
8 |
R. Martin, 'Power-Profiler : Optimizing ASICs Power Consumption at the Behavioral Level,' in Proc. 32nd DAC, June 1995, pp.42-47
|
9 |
A. Chandrakasan, R. Brodersen, 'Minimizing Power Consumption in Digital CMOS Circuits,' IEEE Proceedings, vol. 83, no. 4, April 1996, pp.498-523
DOI
ScienceOn
|
10 |
M.C. Johnson and K. Roy,' Datapath scheduling with multiple supply voltages and level converters', ACM Trans. Design Automat. Electron. Syst., vol. 2, no.3, pp.227-248, July 1997
DOI
|
11 |
A. Raghunathan and N. K. Jha, 'Behavioral synthesis for low power, in Proc. IEEE design Automation conf, 1995
|
12 |
J. Chang, 'Register Allocation and Binding for Low Power, in Proc. 32nd DAC, June 1995, pp.29-35
|
13 |
A. Chandrakasan et aI., 'Low-Power CMOS Digital Design,' J. Solid-State Circuits, vo1.27, no.4, April 1992, pp.473-484
DOI
ScienceOn
|
14 |
A. chandraksan, M. Potkonjak, R. Mehra, J. Rabaey, and Brodersen, "Optimizing power using transformations,' IEEE Trans. Computer-Aided design, vol. 14, pp.12-31, Jan. 1995
DOI
ScienceOn
|
15 |
e. Musoll and J. Cortadella, "High-level synthesis techniques for reducing the activity of functional unit ," in Proc. Int. Symp. Low Power Design, 1995, pp. 99-104
|
16 |
A. Ghosh, "Estimation of Average Switching Activity in Combination and Sequential Circuits", in Proc. 29th DAC, June 1992, pp.253-259
|