Low Power Force-Directed scheduling for Optimal module selection Architecture Synthesis

최적 모듈 선택 아키텍쳐 합성을 위한 전력 감소 Force-Directed 스케쥴링

  • 최지영 (제천기능대학 정보통신설비과) ;
  • 김희석 (청주대학교 전자공학과)
  • Published : 2004.09.01

Abstract

In this paper, we present a reducing power conswnption of a scheduling for module selection under the time constraint. The proposed low power scheduling executes FDS_LP considering low power to exist the FDS scheduling by inputted the behavioral language. The proposed FDS_LP perfonns lower power consumption with dynamic power which is minimized the switching activity, based on force conception In the time step of module selection, an optimal RT(Register Transfer) library is composed by exploration of the parameters such as power, area, and delay. To find optimal parameters of RT library, an optimal module selection algorithm using Branch and Bound algorithm is also proposed. In the comparison and experimental results, The proposed FDS_LP algorithm reduce maximum power saving up to 23.9% comparing to previous FDS algorithm.

본 논문은 최적 모듈 선택 아키텍쳐 합성을 위한 천력 감소 Force-directed 스케줄링을 제안한다. 제안한 전력 강소 스케줄링은 행위 수준 언어를 업력으로 스위칭 활동-(switching activity) 을 고려하여 기존의 FDS 스케쥴링을 저 전력으로 고려한 FDS_LP 앙고리듬을 수행한다. 제안한 FDSL LP 알고리듬은 스위칭 활동을 최소로 하는 동적 파워를 포스 개념에 적용하여 전력 감소를 수행한다. 모듈 선택에서는 전력, 면적, 지연의 매개 변수를 고려하여 최척 모율 성택 RT 라이브러리를 구축한다. 구축한 RT 라이브러리에서 최적 파라메터를 구하기 위해서 프렌치 앤드 바운드 방법을 사용한 최걱 요율 선택 방법을 제안한다. 비교 실험에서는 최적 모율 선택을 고려한 제안한 FDS LP 앙고리듬과 기존의 FDS 알고리듬간의 전력 차이를 비교하여 최대 23.9 % 까지 전력 감소를 얻을 수 있다.

Keywords

References

  1. R. Hartley, 'Behavioral to Structural Translation in a Bit-Serial Silicon Compiler,' IEEE Trans. CAD, vol. 7. no. 8, Aug. 1988, pp.877-886
  2. A. Chandrakasan, R. Brodersen, 'Minimizing Power Consumption in Digital CMOS Circuits,' IEEE Proceedings, vol. 83, no. 4, April 1996, pp.498-523 https://doi.org/10.1109/5.371964
  3. A. Chandrakasan et aI., 'Low-Power CMOS Digital Design,' J. Solid-State Circuits, vo1.27, no.4, April 1992, pp.473-484 https://doi.org/10.1109/4.126534
  4. A. Ghosh, "Estimation of Average Switching Activity in Combination and Sequential Circuits", in Proc. 29th DAC, June 1992, pp.253-259
  5. P. Landman, Power Estimation of High-Level Synthesis', in Proc. European DAC, Feb. 1993, pp.361-366
  6. A. Chandarksan et aI., 'HYPER-LP: A System fo Power Minimization Using Architecture Transformation,' in Proc. ICCAD, Nov. 1992, pp.300-303
  7. R. Martin, 'Power-Profiler : Optimizing ASICs Power Consumption at the Behavioral Level,' in Proc. 32nd DAC, June 1995, pp.42-47
  8. J. Chang, 'Register Allocation and Binding for Low Power, in Proc. 32nd DAC, June 1995, pp.29-35
  9. A. chandraksan and R. Brodersen, 'Minimizing power consumption in digital CMOS circuit." in Proc. IEEE, vol.83, Apr. 1995, pp.498-523 https://doi.org/10.1109/5.371964
  10. A. chandraksan, M. Potkonjak, R. Mehra, J. Rabaey, and Brodersen, "Optimizing power using transformations,' IEEE Trans. Computer-Aided design, vol. 14, pp.12-31, Jan. 1995 https://doi.org/10.1109/43.363126
  11. A. Dasgupta and R. Karri, 'Simultaneous scheduling and binding for low power minimization during microarchitecture synthesis,' in Proc. Int. symp. Low-Power design, Apr.1995, pp.69-74
  12. A. Raghunathan and N. K. Jha, 'Behavioral synthesis for low power, in Proc. IEEE design Automation conf, 1995
  13. e. Musoll and J. Cortadella, "High-level synthesis techniques for reducing the activity of functional unit ," in Proc. Int. Symp. Low Power Design, 1995, pp. 99-104
  14. H.Singh and D. D. Gajski, 'A Design Methodology for Behavioral Level Power Exploradon: Implementation and Experiments',Technical Report 397-28, University ofCalifornia, lrvine, 1997
  15. J.-M. Chang and M. Pedram,' Energy minimization using multiple supply voltage',IEE E Trans. VLSI Syst., vol. 5, Dec. 1997
  16. M.C. Johnson and K. Roy,' Datapath scheduling with multiple supply voltages and level converters', ACM Trans. Design Automat. Electron. Syst., vol. 2, no.3, pp.227-248, July 1997 https://doi.org/10.1145/264995.264997