• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.16 no.6
• /
• pp.465-471
• /
• 2023

This paper proposes a comparator structure that improves the noise and output delay of a single-slope ADC(SS-ADC) used in CMOS Image Sensor (CIS). To improve the noise and delay characteristics of the output, a comparator structure using the miller effect is designed by inserting a capacitor between the output node of the first stage and the output node of the second stage of the comparator. The proposed comparator structure improves the noise, delay of the output, and layout area by using a small capacitor. The CDS counter used in the single slop ADC is designed using a T-filp flop and bitwise inversion circuit, which improves power consumption and speed. The single-slope ADC also performs dual CDS, which combines analog correlated double sampling (CDS) and digital CDS. By performing dual CDS, image quality is improved by reducing fixed pattern noise (FPN), reset noise, and ADC error. The single-slope ADC with the proposed comparator structure is designed in a 0.18-㎛ CMOS process.

• Journal of Power Electronics
• /
• v.16 no.3
• /
• pp.1226-1235
• /
• 2016

For wearable health monitoring systems, a fundamental problem is the limited space for storing energy, which can be translated into a short operational life. In this paper, a highly efficient active voltage doubling rectifier with a wide input range for micro-piezoelectric energy harvesting systems is proposed. To obtain a higher output voltage, the Dickson charge pump topology is chosen in this design. By replacing the passive diodes with unbalanced-biased comparator-controlled active counterparts, the proposed rectifier minimizes the voltage losses along the conduction path and solves the reverse leakage problem caused by conventional comparator-controlled active diodes. To improve the rectifier input voltage sensitivity and decrease the minimum operational input voltage, two low power common-gate comparators are introduced in the proposed design. To keep the comparator from oscillating, a positive feedback loop formed by the capacitor C is added to it. Based on the SMIC 0.18-μm standard CMOS process, the proposed rectifier is simulated and implemented. The area of the whole chip is 0.91×0.97 mm², while the rectifier core occupies only 13% of this area. The measured results show that the proposed rectifier can operate properly with input amplitudes ranging from 0.2 to 1.0V and with frequencies ranging from 20 to 3000 Hz. The proposed rectifier can achieve a 92.5% power conversion efficiency (PCE) with input amplitudes equal to 0.6 V at 200 Hz. The voltage conversion efficiency (VCE) is around 93% for input amplitudes greater than 0.3 V and load resistances larger than 20kΩ.

• Proceedings of the KIEE Conference
• /
• 2006.10c
• /
• pp.606-608
• /
• 2006

This paper describes a 8bit 10MS/s low power pipelined analog-to-digital converter(ADC). To reduce power consumption in proposed ADC, a high gain op-amp that consumes large power in MDAC(multiplying DAC) of conventional pipelined ADC is replaced with simple comparator and current sources. Moreover, differential charge transfer amplifier technique with latch in the sub-ADC reduces the power consumption to less than half compared with the conventional sub-ADC which use high speed comparator. The proposed ADC shows the power consumption of 1.8mW at supply voltage of 1.8V. This proposed ADC is suitable to apply to the portable display device. The circuit was implemented with 0.18um CMOS technology and the core size of circuit is 2.5mm${\times}$1mm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2017.10a
• /
• pp.429-432
• /
• 2017

In this paper, a full - wave rectifying harvesting circuit with a high-performance comparator is designed. Designed circuits are divided into Negative Voltage Converter and Active Diode stages. The comparator included in the active diode stage is implemented as a 3-stage type and divided into pre-amplification, decision circuit, and output buffer stages. The main purpose of this comparator is to reduce the propagation delay and improve the voltage and power efficiency of the harvesting circuit. The proposed circuit is designed with magna $0.35{\mu}m$ CMOS process and its operation is verified by simulation. The chip area of the designed energy harvesting circuit is $900{\mu}m{\times}712{\mu}m$.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.1A
• /
• pp.1-8
• /
• 2004

Viterbi decoders are widely used for communication and high-density storage devices. An add-compare-select(ACS) unit has been an active research area for a long time because it is the most critical component in determining the operation speed and power-consumption of the Viterbi decoder. We propose a new comparator which is faster and consumes less power than existing ones. We also used the new comparator for a Viterbi decoder and our simulations results show the Viterbi decoder outperforms existing ones at least $20\%$ in its operating speed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2012.05a
• /
• pp.88-90
• /
• 2012

This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with a rail-to-rail input range. The proposed SAR ADC consists of a capacitor digital-analog converter (DAC), a SAR logic and a comparator. To reduce the frequency of an external clock, the internal clock which is asynchronously generated by the SAR logic and the comparator is used. The time-domain comparator with a offset calibration technique is used to achieve a high resolution. To reduce the power consumption and area, a split capacitor-based differential DAC is used. The designed asynchronous SAR ADC is fabricated by using a 0.18 um CMOS process, and the active area is $420{\times}140{\mu}m^2$. It consumes the power of 0.818 mW with a 1.8 V supply and the FoM is 91.8 fJ/conversion-step.

• Journal of IKEEE
• /
• v.25 no.1
• /
• pp.206-211
• /
• 2021

This paper proposes a Self-Reset Zero-Current Switching (ZCS) Circuit for thermoelectric energy harvesting. The Self-Reset ZCS circuit minimizes the operating current consumed by the voltage comparator, thereby reduces the power consumption of the energy harvesting circuit and improves the energy conversion efficiency by adding the self-reset function to the comparator. The Self-Reset ZCS circuit shows 3.4% of improvement in energy efficiency compared to the energy harvesting system with the conventional analog comparator ZCS for the output/input voltage ratio of 5.5 as a result of circuit simulation. The proposed circuit is useful for improving the performance of the wearable and bio-health-related harvesting circuits, where low-power and energy-efficient thermoelectric energy harvesting is needed.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.54 no.11
• /
• pp.503-507
• /
• 2005

Both ratio error and phase angle error in voltage transformer(VT) depend on values of VT burden used. Thus, precise measurement of burden is very important for the evaluation of VT. A method of evaluation for VT burden has been developed by employing the portable decade resistor, with AC-DC resistance difference less than 10-3. The burden value(value and power factor) can be obtained by conductance and susceptance, obtained by measuring the change of ratio error and phase angle error caused by the resistance change of decade resistor. The burden value and power factor obtained by the method are consistent with those obtained using power analyzer within corresponding uncertainties.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.6
• /
• pp.1250-1259
• /
• 2012

In this paper, a time-domain comparator is proposed for a successive approximation (SA) analog-to-digital converter (ADC) with a low power and high resolution. The proposed time-domain comparator consists of a voltage-controlled delay converter with a clock feed-through compensation circuit, a time amplifier, and binary phase detector. It has a small input capacitance and compensates the clock feed-through noise. To analyze the performance of the proposed time-domain comparator, two 1V 10-bit 200-kS/s SA ADCs with a different time-domain comparator are implemented by using 0.18-${\mu}m$ 1-poly 6-metal CMOS process. The measured SNDR of the implemented SA ADC is 56.27 dB for the analog input signal of 11.1 kHz, and the clock feed-through compensation circuit and time amplifier of the proposed time-domain comparator enhance the SNDR of about 6 dB. The power consumption and area of the implemented SA ADC are 10.39 ${\mu}W$ and 0.126 mm2, respectively.

• Proceedings of the KIEE Conference
• /
• 2001.07b
• /
• pp.1035-1037
• /
• 2001

This paper presents an improved hys- teresis current control method for three-phase PWM power inverters using 3-level comparator. Hysteresis current controller using 3-level comparator has an advantage of constant switching frequency compared with conventional hysteresis current controller. However, this method has disadvantage that the longer sampling period, the larger current error because the switching is performed without considering current error magnitude of each phase. The proposed method improves the control performance by selecting the optimum switching pattern in which the magnitudes of current errors are considered introducing space vector concept. Simulation results using Matlab/Simulink show that the proposed control method reduces current error keeping the merit of previous hysteresis current control method.