• The KIPS Transactions:PartA
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• v.14A no.1 s.105
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• pp.47-54
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• 2007

In this paper we present a translation lookaside buffer (TLB) system with low power consumption for imbedded processors. The proposed TLB is constructed as multiple banks, each with an associated block buffer and a corresponding comparator. Either the block buffer or the main bank is selectively accessed on the basis of two bits in the block buffer (tag buffer). Dynamic power savings are achieved by reducing the number of entries accessed in parallel, as a result of using the tag buffer as a filtering mechanism. The performance overhead of the proposed TLB is negligible compared with other hierarchical TLB structures. For example, the two-cycle overhead of the proposed TLB is only about 1%, as compared with 5% overhead for a filter (micro)-TLB and 14% overhead for a same structure without continuos accessing distinction algorithm. We show that the average hit ratios of the block buffers and the main banks of the proposed TLB are 95% and 5% respectively. Dynamic power is reduced by about 95% with respect to with a fully associative TLB, 90% with respect to a filter-TLB, and 40% relative to a same structure without continuos accessing distinction algorithm.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.4
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• pp.338-347
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• 2021

In this paper, the beta-ray sensor circuit used in the true random number generator was designed using DB HiTek's 0.18㎛ CMOS process. The CSA circuit proposed a circuit having a function of selecting a PMOS feedback resistor and an NMOS feedback resistor, and a function of selecting a feedback capacitor of 50fF and 100fF. And for the pulse shaper circuit, a CR-RC2 pulse shaper circuit using a non-inverting amplifier was used. Since the OPAMP circuit used in this paper uses single power instead of dual power, we proposed a circuit in which the resistor of the CR circuit and one node of the capacitor of the RC circuit are connected to VCOM instead of GND. And since the output signal of the pulse shaper does not increase monotonically, even if the output signal of the comparator circuit generates multiple consecutive pulses, the monostable multivibrator circuit is used to prevent signal distortion. In addition, the CSA input terminal, VIN, and the beta-ray sensor output terminal are placed on the top and bottom of the silicon chip to reduce capacitive coupling noise between PCB traces.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.2 s.332
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• pp.61-74
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• 2005

Digital Multimedia Broadcasting(DMB) is a reliable multi-service system for reception by mobile and portable receivers. DMB system allows interference-free reception under the conditions of multipath propagation and transmission errors using COFDM modulation scheme, simultaneously, needs powerful channel error's correction ability. Viterbi Decoder for DMB receiver uses punctured convolutional code and needs lots of computations for real-time operation. So, it is desired to design a high speed and low-power hardware scheme for Viterbi decoder. This paper proposes a combined add-compare-select(ACS) and path metric normalization(PMN) unit for computation power. The proposed PMN architecture reduces the problem of the critical path by applying fixed value for selection algorithm due to the comparison tree which has a weak point from structure with the high-speed operation. The proposed ACS uses the decomposition and the pre-computation technique for reducing the complicated degree of the adder, the comparator and multiplexer. According to a simulation result, reduction of area $3.78\%$, power consumption $12.22\%$, maximum gate delay $23.80\%$ occurred from punctured viterbi decoder for DMB system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.9
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• pp.1087-1093
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• 2012

In this paper, we implemented a HF-band magnetic-field communication system consisting of an amplitude shift keying(ASK) transmitter, a pair of loop antennas, and an ASK receiver. Especially, we suggested a new ASK transmitter architecture, where a drain bias of class E amplifier is switched alternatively between two voltage levels with respect to input data. A maximum 5 W class E amplifier was designed using a low cost IRF510 power MOSFET at the frequency of 6.78 MHz. A measured sensitivity of the designed ASK receiver is -78 dBm, which consists of a log amplifier, a filter, and a comparator. Maximum communication range of magnetic-wave communication system with loop antennas was calculated using magnetic field equations in both near-field and far-field ranges. Also, in order to verify the calculated values, an indoor propagation loss was measured using a pair of loop antennas whose dimensions are $30{\times}30cm$. Maximum operating range is estimated about 35 m in case of transmitter's output power of 1 W and receiver sensitivity of -70 dBm, respectively. Finally, the communication field test using the designed ASK transmitter and receiver was successfully done at the distance of 5 m.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.1
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• pp.129-134
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• 2014

This paper presents a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) which consists of a digital-to-analog converter (DAC), a SAR logic, and a comparator. The designed asynchronous SAR ADC with a rail-to-rail input range uses a binary weighted DAC using metal-oxide-metal (MOM) capacitor to improve sampling rate. The proposed 10-bit 10-MS/s asynchronous SAR ADC is fabricated using a 0.18-${\mu}m$ CMOS process and its active area is $0.103mm^2$. The power consumption is 0.37 mW when the voltage of supply is 1.1 V. The measured SNDR are 54.19 dB and 51.59 dB at the analog input frequency of 101.12 kHz and 5.12 MHz, respectively.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.11
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• pp.5403-5408
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• 2012

In this paper, we introduce the multiple frequency bio-electrical impedance analysis method for body composition analysis. And then we implement the multiple frequency bio-electrical impedance analysis system. Overall system consists of: multiple frequency alternating current signal generator contained alternating current signal, phase signal detector, voltage signal detector, micro controller, in-out device(key-pad LCD), conductivity electrodes, system power. We explain the architecture of the system and required theory to implement the system. In order to investigate the clinical significance of the body composition data, compare to the data measured by the expert body composition analyzer which provide high reproduction and precision. Finally, experimental results which are the correlation between the measured data show the very high reproduction performance of the body composition analysis in the proposed system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.1
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• pp.53-60
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• 2010

This paper presents a novel gain control system composed of a feedback circuit, Two stage Low Noise Amplifier (LNA) using 0.18 um CMOS technology for 5.2 GHz. The feedback circuit consists of the seven function blocks: peak detector, comparator, ADC, IVE(Initial Voltage Elimination) circuit, switch, storage, and current controller. We focus on detecting signal and designing storage circuit that store the previous state. The power consumption of the feedback circuit in the system can be reduced without sacrificing the gain by inserting the storage circuit. The adaptive front-end system with the feedback circuit exhibits 11.39~22.74 dB gain, and has excellent noise performance at high gain mode. Variable gain LNA consumes 5.68~6.75 mW from a 1.8 V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.61-66
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• 2008

Recently, portable devices which require small area and low power consumption employ applications using 3D graphics such as 3D games and 3D graphical user interfaces. We propose an efficient clipping engine algorithm which is suitable in 3D graphics pipeline. The clipping operation is divided into two steps: one is the selection process in the transformation engine and the other is the pixel clipping process in the scan conversion unit. The clipping operation is possible with addition of simple comparator. The clipping for the Y-axis is achieved in the edge walk stage and that for the X and Z-axis is performed in the span processing. The proposed clipping algorithm reduces the operation cycles and the area of of 3D graphics pipelines. We designed a 3D graphics pipeline with the proposed clipping algorithm using Verilog-HDL and verifies the operation using an FPGA.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.1 s.92
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• pp.49-55
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• 2005

In this paper, the phase locked harmonic oscillator(PLHO) using the analog PLL(Phase Locked Loop) is designed and implemented for a wireless LAN system. The harmonic oscillator is consisted of a ring resonator, a varactor diode and a PLL circuit. Because the fundamental fiequency of 8.5 GHz is used as the feedback signal for the PLL and the 2nd harmonic of 17.0 GHz is used as the output, a analog frequency divider for the phase comparison in the PLL system can be omitted. For the simple PLL circuit, the SPD(Sampling Phase Detector) as a phase comparator is used. The output power of the phase locked harmonic oscillator is 2.23 dBm at 17 GHz. The fundamental and 3rd harmonic suppressions are -31.5 dBc and -29.0 dBc, respectively. The measured phase noise characteristics are -87.6 dBc/Hz and -95.4 dBc/Hz at the of offset frequency of 1 kHz and 10 kHz from the carrier, respectively.

• Journal of IKEEE
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• v.17 no.3
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• pp.284-293
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• 2013

This paper describes a DC-DC boost converter for thermoelectric energy harvesting. The designed converter boosts the VDD through a start-up block from a low-output voltage of a thermoelectric device and the boosted VDD is used to operate the internal control block. When the VDD reaches a predefined value, a detector circuit makes the start-up block turn off to minimize current consumption. The final boosted VOUT is achieved by alternately operating the DC-DC converter for VDD and the main DC-DC converter for VOUT according to the comparator outputs. Simulation results shows that the designed converter generates 2.65V from an input voltage of 200mV and its maximum power efficiency is 63%. The area of the chip designed using a 0.35um CMOS process is $1.3mm{\times}0.7mm$ including pads.