• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.2
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• pp.75-79
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• 2009

A system-on-a-chip communication architecture has a significant impact on the performance and power consumption of modern multi-processors system-on-chips (MPSoCs). However, customization of such architecture for a specific application requires the exploration of a large design space. Thus, system designers need tools to rapidly explore and evaluate communication architectures. In this paper we present the method for application-specific low-power bus architecture synthesis at system-level. Our paper has two contributions. First, we build a bus power model of AMBA AXI bus communication architecture. Second, we incorporate this power model into a low-power architecture exploration algorithm that enables system designers to rapidly explore the target bus architecture. The proposed exploration algorithm reduces power consumption by 20.1% compared to a maximally connected reduced matrix, and the area is also reduced by 20.2% compared to the maximally connected reduced matrix.

• International Journal of Naval Architecture and Ocean Engineering
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• v.11 no.2
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• pp.765-781
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• 2019

This study predicts the power consumption of an Electric Propulsion Ship (EPS) in marine environment. The EPS is driven by a propeller rotated by a propulsion motor, and the power consumption of the propeller changes by the marine environment. The propulsion motor consumes the highest percentage of the ships' total power. Therefore, it is necessary to predict the power consumption and determine the power generation capacity and the propeller capacity to design an efficient EPS. This study constructs a power estimation simulator for EPS by using a ship motion model including marine environment and an electric power consumption model. The usage factor that represents the relationship between power consumption and propulsion is applied to the simulator for power prediction. Four marine environment scenarios are set up and the power consumed by the propeller to maintain a constant ship speed according to the marine environment is predicted in each scenario.

• Journal of the Korean Society of Systems Engineering
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• v.14 no.1
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• pp.83-88
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• 2018

Engineering is a sector with more than three times the industrial effectiveness of manufacturing. In the domestic engineering life cycle, the Operations & Maintenance (O&M) phase is a relatively high level of technology. Based on accumulated knowledge of O&M phase, it is necessary to advance operating technology and expand overseas O&M market expenditure. This study is the early stage of knowledge-based power plant O&M service framework reference model. In this study, we propose a conceptual model of architecture framework for power plant O&M. We survey the architecture framework and reference model and propose conceptual model of architecture framework for power plant O&M. The conceptual model of architecture framework for power plant O&M consists of stakeholder, O&M scenario, O&M technology. In particular, the O&M technology is defined as the fourth industrial revolution intelligence information technology. We defined a meta model from the conceptual model to define the power plant O&M architecture framework. In the future, we intend to development an architecture framework from the conceptual model and meta model.

• Structural Engineering and Mechanics
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• v.12 no.4
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• pp.449-457
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• 2001

In the design of industrial chimneys and towers, structural engineers must assume a level of the inherent damping in the structures. In order to better estimate the dynamic response of those structures, actual damping was measured from wind-induced vibration signals of chimneys and towers and its characteristics with respect to the response levels, the structural systems, and the wind direction were discussed. Damping ratio and natural frequency for three chimneys and two towers were calculated using random decrement technique.

• Proceedings of the IEEK Conference
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• 2000.11d
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• pp.127-130
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• 2000

This paper proposes a low-Power DDC(Digital Down Converters) architecture for IF(Intermediate frequency) signal processing. It is shown that concept of conventional interpolated FIR filters can be expanded to IIR filters for DDC applications. Also in the paper, power dissipations for the proposed architecture and conventional ones are estimated.

• IEMEK Journal of Embedded Systems and Applications
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• v.8 no.4
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• pp.195-204
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• 2013

The embedded software has been developed in the forms of various versions that provides similar service based on product family. For increase usefulness of product family, software must has well-structured and reusable properties. Software architecture is important to improve adaptability in model-based development of embedded software mounted onto product family. In this paper, we proposed a technique of ADD(Attribute-Driven Design)-based software architecture design for low power software development. This technique provides a chance to consider the power consumption issue in design phase of software, and makes possible to develop low power embedded software.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.736-744
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• 2016

Network on chip (NoC) is an emerging technology in the field of multi core interconnection architecture. The routers plays an essential components of Network on chip and responsible for packet delivery by selecting shortest path between source and destination. State-of-the-art NoC designs used routing table to find the shortest path and supports four ports for packet transfer, which consume high power consumption and degrades the system performance. In this paper, the multi port multi core router architecture is proposed to reduce the power consumption and increasing the throughput of the system. The shared buffer is employed between the multi ports of the router architecture. The performance of the proposed router is analyzed in terms of power and current consumption with conventional methods. The proposed system uses Modelsim software for simulation purposes and Xilinx Project Navigator for synthesis purposes. The proposed architecture consumes 31 mW on CPLD XC2C64A processor.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.863-866
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• 2005

Low-power design is one of the most important challenges encountered in maximizing battery life in portable devices as well as saving energy during system operation. In this paper we propose a low-power DCT (Discrete Cosine Transform) architecture using a modified Computation Sharing Multiplication (CSHM). The overall rate of power consume is reduced during DCT: the proposed architecture does not perform arithmetic operations on unnecessary bits during the Computation Sharing Multiplication calculations. Experimental results show that it is possible to reduce power dissipation up to about $7{\sim}8%$ without compromising the final DCT results. The proposed lowpower DCT architecture can be applied to consumer electronics as well as portable multimedia systems requiring high throughput and low-power.

• 한국태양에너지학회:학술대회논문집
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• 2011.04a
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• pp.42-47
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• 2011

This study aims to choose installation location of wind power system and analyze influence factors of wind power system by shape of super high-raise building by using CFD simulation. As a result of this study, wind power system is more applicable to streamlined building than normal building. Round openings are seemed to be the most efficient shape for building integrated wind power system in types applying venturi effect. Safety and vibration should be considered in the case of application of wind power system between the buildings.

• ETRI Journal
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• v.37 no.4
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• pp.772-779
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• 2015

This paper presents a power-efficient hardware realization for a motion estimation technique that is based on the full-search block matching algorithm (FSBMA). The considered input is the quarter common intermediate format of digital video. The mean of absolute difference (MAD) is the distortion criteria employed for the block matching process. The conventional architecture considered for the hardware realization of FSBMA is that of the shift register-based 2-D systolic array. For this architecture, a conservative approximation technique is adapted to eliminate unnecessary MAD computations involved in the block matching process. Upon introducing the technique to the conventional architecture, the power and complexity of its implantation is reduced, while the accuracy of the motion vector extracted from the block matching process is preserved. The proposed architecture is verified for its functional specifications. A performance evaluation of the proposed architecture is carried out using parameters such as power, area, operating frequency, and efficiency.