• Journal of Sensor Science and Technology
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• v.33 no.3
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• pp.147-151
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• 2024

The importance of Wireless Sensor Networks is becoming more evident owing to their practical applications in various areas. However, the energy problem remains a critical barrier to the progress of WSNs. By reducing the energy consumed by the sensor nodes that constitute WSNs, the performance and lifespan of WSNs will be enhanced. In this study, we introduce an energy-efficient ternary modulator that employs multi-threshold CMOS for logic conversion. We optimized the design with a low-power ternary gate structure based on a pass transistor using the MTCMOS process. Our design uses 71.69% fewer transistors compared to the previous design. To demonstrate the improvements in our design, we conducted the HSPICE simulation using a CMOS 180 nm process with a 1.8V supply voltage. The simulation results show that the proposed ternary modulator is more energy-efficient than the previous modulator. Power-delay product, a benchmark for energy efficiency, is reduced by 97.19%. Furthermore, corner simulations demonstrate that our modulator is stable against PVT variations.

• Transactions on Electrical and Electronic Materials
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• v.15 no.6
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• pp.328-332
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• 2014

Thin film transistors (TFTs) with an amorphous silicon zinc tin oxide (a-2SZTO) channel layer have been fabricated using an RF magnetron sputtering system. The effect of the change of excitation electron on the variation of the total interfacial trap states of a-2SZTO systems was investigated depending on sputtering power, since the interfacial state could be changed by changing sputtering power. It is well known that Si can effectively reduce the generation of the oxygen vacancies. However, The a-2SZTO systems of ZTO doped with 2 wt% Si could be degraded because the Si peripheral electron belonging to a p-orbital affects the amorphous zinc tin oxide (a-ZTO) TFTs of the s-orbital overlap structure. We fabricated amorphous 2 wt% Si-doped ZnSnO (a-2SZTO) TFTs using an RF magnetron sputtering system. The a-2SZTO TFTs show an improvement of the electrical property with increasing power. The a-2SZTO TFTs fabricated at a power of 30 W showed many of the total interfacial trap states. The a-2SZTO TFTs at a power of 30 W showed poor electrical property. However, at 50 W power, the total interfacial trap states showed improvement. In addition, the improved total interfacial states affected the thermal stress of a-2SZTO TFTs. Therefore, a-2SZTO TFTs fabricated at 50 W power showed a relatively small shift of threshold voltage. Similarly, the activation energy of a-2SZTO TFTs fabricated at 50 W power exhibits a relatively large falling rate (0.0475 eV/V) with a relatively high activation energy, which means that the a-2SZTO TFTs fabricated at 50 W power has a relatively lower trap density than other power cases. As a result, the electrical characteristics of a-2SZTO TFTs fabricated at a sputtering power of 50 W are enhanced. The TFTs fabricated by rf sputter should be carefully optimized to provide better stability for a-2SZTO in terms of the sputtering power, which is closely related to the interfacial trap states.

• Journal of Electrical Engineering and Technology
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• v.12 no.5
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• pp.1805-1811
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• 2017

Recently, DC systems are considered as efficient electric power systems for renewable energy based clean power generators. This discloses several critical issues that are required to be considered before the installation of the DC systems. First of all, voltage/current switching stress, which is aggravated by large fault current, might damage DC circuit breakers. This problem can be simply solved by applying a superconducting fault current limiter (SFCL) as proposed in this study. It allows a simple use of insulated-gate bipolar transistors (IGBTs) as a DC circuit breaker. To evaluate the proposed resistive type SFCL application to the DC circuit breaker, a DC distribution system is composed of the practical line impedances from the real distribution system in Do-gok area, Korea. Also, to reflect the distributed generation (DG) effects, several DC-to-DC converters are applied. The locations and sizes of the DGs are optimally selected according to the results of previous studies on DG optimization. The performance of the resistive type SFCL applied DC circuit breaker is verified by a time-domain simulation based case study using the power systems computer aided design/electromagnetic transients including DC (PSCAD/ EMTDC(R)).

• Journal of information and communication convergence engineering
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• v.13 no.3
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• pp.180-188
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• 2015

As a potential alternative to the complementary metal-oxide semiconductor (CMOS) technology, many researchers are focusing on carbon-nanotube field-effect transistors (CNFETs) for future electronics. However, existing studies report the advantages of CNFETs over CMOS at the device level by using small-scale circuits, or over outdated CMOS technology. In this paper, we propose a methodology of analyzing CNFET-based circuits and study its impact at the full-chip scale. First, we design CNFET standard cells and use them to construct large-scale designs. Second, we perform parasitic extraction of CNFET devices and characterize their timing and power behaviors. Then, we perform a full-chip analysis and show the benefits of CNFET over CMOS in 45-nm and 20-nm designs. Our full-chip study shows that in the 45-nm design, CNFET circuits achieve a 5.91×/3.87× (delay/power) benefit over CMOS circuits at a density of 200 CNTs/µm. In the 20-nm design, CNFET achieves a 6.44×/3.01× (delay/power) benefit over CMOS at a density of 200 CNTs/µm.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.248-249
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• 2008

ZnO (Zinc Oxide) thin film can be applied to various devices. Recently, ZnO film has been promoted in transparent TFTs (thin film transistors) because of high transparency and low temperature process. In this paper, ZnO thin films were grown on glass with the three conditions of RF sputtering power, which are 50W, 75W, 100W. Their structural, electrical and optical properties were investigated by using XRD, UV-Visible spectrometer and 4-point probes. In the ZnO film with 50W process, good crystallinity, high transmittance, and high sheet resistance were shown. In conclusion, the ZnO film with 50W can be an optimal channel layer of TFTs.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.495-498
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• 2006

This paper reports a high power 60 GHz push-push oscillator fabricated using 0.12 um metamorphic high electron-mobility transistors (mHEMTs). The devices with a $0.1{\mu}m$ gate-length exhibited good DC and RF characteristics such as a maximum drain current of 700 mA/mm, a peak gm of 660 mS/mm, and an $f_T$ of 170 GHz. By combining two sub-oscillators having $6{\times}50{\mu}m$ periphery mHEMT, the push-push oscillator achieved a 6.3 dBm of output power at 59.5 GHz with more than -35 dBc fundamental suppression. This is one of the highest output power obtained using mHEMT technology without buffer amplifier, and demonstrates the potential of mHEMT technology for cost effective millimeter-wave commercial applications.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.443-450
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• 2016

The linearization technique for low noise amplifier (LNA) has been implemented in standard $0.18-{\mu}m$ BiCMOS process. The MOS-BJT derivative superposition (MBDS) technique exploits a parallel LC tank in the emitter of bipolar transistor to reduce the second-order non-linear coefficient ($g_{m2}$) which limits the enhancement of linearity performance. Two feedback capacitances are used in parallel with the base-collector and gate-drain capacitances to adjust the phase of third-order non-linear coefficients of bipolar and MOS transistors to improve the linearity characteristics. The MBDS technique is also employed cascode configuration to further reduce the second-order nonlinear coefficient. The proposed LNA exhibits gain of 9.3 dB and noise figure (NF) of 2.3 dB at 2 GHz. The excellent IIP3 of 20 dBm and low-power power consumption of 5.14 mW at the power supply of 1 V are achieved. The input return loss ($S_{11}$) and output return loss ($S_{22}$) are kept below - 10 dB and -15 dB, respectively. The reverse isolation ($S_{12}$) is better than -50 dB.

• Proceedings of the KIEE Conference
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• 2003.07b
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• pp.1169-1171
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• 2003

This paper presents a 1.6[kW]class single phase high power factor(HPF) pulse width modulation(PWM) boost rectifier featuring soft commutation of the active switches at zero current. It incorporates the most desirable properties of conventional PWM and soft switching resonant techniques. The input current shaping is achieved with average current mode control and continuous inductor current mode. This new PWM converter provides zero current turn on and turn off of the active switches, and it is suitable for high power applications employing insulated gate bipolar transistors(IGBT'S). The principle of operation, the theoretical analysis, a design example, and experimental results from laboratory prototype rated at 1.6[kW] with 400[Vdc] output voltage are presented. The measured efficiency and the power factor were 96.2[%] and 0.99[%], respectively, with an input current Total Harmonic Distortion(THD) equal to 3.94[%], for an input voltage with THD equal to 3.8[%], at rated load.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.10A
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• pp.1582-1589
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• 2000

A dynamic D-flipflop is proposed aiming at low power and high frequency(GHz) operations. The proposed D-flipflop uses a smaller number of pmos transistors that it operates high speed in same dimensions. Also, it consumes lower power than conventional approaches by a shared nmos with clock input. In order to compare the performance of the proposed D-flipflop, we perform simulation estimating power consumption and maximum operating frequency of each same dimension D-flipflop. A high speed dual-modulus prescaler employing the proposed D-flipflop. A high speed dual-modulus prescaler employing the proposed D-flipflop. A high speed dual-modulus prescaler employing the proposed D-flipflop is evaluated via the same method. The simulation results show that the proposed D-fliplflop has good performance than conventional circuits.

• Proceedings of the KIEE Conference
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• 2001.10a
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• pp.180-182
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• 2001

Input Current Correction of Single-Phase Buck Rectifier is studied in the paper. To sinusoidal waveform the input current with a near-unity power factor over a wide variety of operating conditions, the output capacitor is operated with voltage reversibility for the supply by arranging the auxiliary diode and power switching device. Then the output voltage is superposed on the input voltage during on time duration of power switching devices in order to minimize the input current distortion caused by the small input voltage when changing the polarity. The tested setup, using two insulated-gate bipolar transistors(IGBT) and a microcomputer, is implemented and IGBT are switched with 20[kHz], which is out of the audible band. Moreover, a rigorous state-space analysis is introduced to predict the operation of the rectifier. The simulated results confirm that the input current can be sinusoidal waveform with a near-unity power factor and a satisfactory output voltage regulation can be achieved.