• Title/Summary/Keyword: Power Transistors

검색결과 393건 처리시간 0.02초

새로운 단상 3전위 인버터회로의 구성에 관한 연구 (A Study on Composition of A Novel Single Phase 3 Level Inverter Circuit)

  • 이종수;백종현
    • 한국조명전기설비학회지:조명전기설비
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    • 제9권5호
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    • pp.51-56
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    • 1995
  • The transistors of single phase 3 level PWM Inverter compose output power transistors and neutral point clamping transistors, which are NPN transistors. Waveforms of driving signals for this are PWM waves for power transistors and period operating waves for neutral point clamping transistors, which signals made W-type modulation from rectangular and sine wave. The output power transistors operate at ON-time complementary and neutral point clamping transistors operate at OFF-time complementary respectively. Therefore, each transistors operate in half period at parallel. Characteristics of this inverter circuit is parallel switching method about series switching method of general inverter. As modulation of 3 level drive signals made from full-wave rectifier of sine wave and rectangular wave, which are level wave about 3 level of complementary transistor inverter. So, this circuit composed complementary operation inverter of NPN transistors only compare with PNP-NPN complementary inverter, which have high power 3 level inverter of complementary operation.

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Ringing Frequency Extraction Method Based on EMD and FFT for Health Monitoring of Power Transistors

  • Ren, Lei;Gong, Chunying
    • Journal of Power Electronics
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    • 제19권1호
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    • pp.307-315
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    • 2019
  • Condition monitoring has been recognized as an effective and low-cost method to enhance the reliability and improve the maintainability of power electronic converters. In power electronic converters, high-frequency oscillation occurs during the switching transients of power transistors, which is known as ringing. The ringing frequency mainly depends on the values of the parasitic capacitance and stray inductance in the oscillation loop. Although circuit stray inductance is an important factor that leads to the ringing, it does not change with transistor aging. A shift in either the inside inductance or junction capacitance is an important failure precursor for power transistors. Therefore, ringing frequency can be used to monitor the health of power transistors. However, the switching actions of power transistors usually result in a dynamic behavior that can generate oscillation signals mixed with background noise, which makes it hard to directly extract the ringing frequency. A frequency extraction method based on empirical mode decomposition (EMD) and Fast Fourier transformation (FFT) is proposed in this paper. The proposed method is simple and has a high precision. Simulation results are given to verify the ringing analysis and experimental results are given to verify the effectiveness of the proposed method.

Vertical Type Organic Transistors and Flexible Display Applications

  • Kudo, Kazuhiro
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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    • pp.168-169
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    • 2007
  • Organic transistors are promising in the future development of active devices for flexible, low-cost and large-area photoelectric devices. However, conventional organic field-effect transistors have lowspeed, low-power, and relatively high operational voltage. Vertical type transistors show high-speed and high-current characteristics and are suitable for driver elements of flexible displays.

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MBDD를 이용한 저전력 VLSI설계기법 (A Method of Low Power VLSI Design using Modified Binary Dicision Diagram)

  • 윤경용;정덕진
    • 대한전기학회논문지:시스템및제어부문D
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    • 제49권6호
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    • pp.316-321
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    • 2000
  • In this paper, we proposed MBDD(Modified Binary Decision Diagram) as a multi-level logic synthesis method and a vertex of MBDD to NMOS transistors matching. A vertex in MBDD is matched to a set of NMOS transistors. MBDD structure can be achieved through transformation steps from BDD structure. MBDD can represent the same function with less vertices less number of NMOS transistors, consequently capacitance of the circuit can be reduced. Thus the power dissipation can be reduced. We applied MBDD to a full odder and a 4-2compressor. Comparing the 4-2compressor block with other synthesis logic, 31.2% reduction and 19.9% reduction was achieved in numbers of transistors and power dissipation respectively. In this simulation we used 0.8 ${\mu}{\textrm}{m}$ fabrication parameters.

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An L-band Stacked SOI CMOS Amplifier

  • Kim, Young-Gi;Hwang, Jae-Yeon
    • 전기전자학회논문지
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    • 제20권3호
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    • pp.279-284
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    • 2016
  • This paper presents a two stage L-band power amplifier realized with a $0.32{\mu}m$ Silicon-On-Insulator (SOI) CMOS technology. To overcome a low breakdown voltage limit of MOSFET, stacked-FET structures are employed, where three transistors in the first stage amplifier and four transistors in the second stage amplifier are connected in series so that their output voltage swings are added in phase. The stacked-FET structures enable the proposed amplifier to achieve a 21.5 dB small-signal gain and 15.7 dBm output 1-dB compression power at 1.9 GHz with a 122 mA DC current from a 4 V supply. The amplifier delivers a 19.7 dBm. This paper presents a two stage L-band power amplifier realized with a $0.32{\mu}m$ Silicon-On-Insulator (SOI) CMOS technology. To overcome a low breakdown voltage limit of MOSFET, stacked-FET structures are employed, where three transistors in the first stage amplifier and four transistors in the second stage amplifier are connected in series so that their output voltage swings are added in phase. The stacked-FET structures enable the proposed amplifier to achieve a 21.5 dB small-signal gain and 15.7 dBm output 1-dB compression power at 1.9 GHz with a 122 mA DC current from a 4 V supply. The amplifier delivers a 19.7 dBm saturated output power with a 16 % maximum Power Added Efficiency (PAE). A bond wire fine tuning technology enables the amplifier a 23.67 dBm saturated output power with a 20.4 % maximum PAE. The die area is $1.9mm{\times}0.6mm$.

전력용 트랜지스터의 직렬연결시 스윗칭 특성 (The Switching Characteristics of Series-Connected Power Transistors)

  • 서범석;이택기;현동석
    • 대한전기학회논문지
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    • 제41권6호
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    • pp.600-606
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    • 1992
  • The series connection of power switching semiconductor elements is essential when a high voltage converter is made, so researches are being conducted to further develop this technology. In the series connection of power switching semiconductor elements, the main problem is that simultaneous conduction at turn-on and simultaneous blocking at turn-off together with voltage balancing are unattainable because of the difference of their switching characteristics. In this paper a novel series connection algorithm is proposed, which can implement not only the synchronization of the points of turn-on and turn-off time but the dynamic voltage balancing in spite of the difference of each switching characteristics. The proposed method is that the compensated control signal is attained from the voltage feedback signal and applied to the series-connected power transistors independently. Computer simulation and experimental results verify its validity.

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Applications of Nanowire Transistors for Driving Nanowire LEDs

  • Hamedi-Hagh, Sotoudeh;Park, Dae-Hee
    • Transactions on Electrical and Electronic Materials
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    • 제13권2호
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    • pp.73-77
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    • 2012
  • Operation of liquid crystal displays (LCDs) can be improved by monolithic integration of the pixel transistors with light emitting diodes (LEDs) on a single substrate. Conventional LCDs make use of filters to control the backlighting which reduces the overall efficiency. These LCDs also utilize LEDs in series which impose failure and they require high voltage for operation with a power factor correction. The screen of small hand-held devices can operate from moderate brightness. Therefore, III-V nanowires that are grown along with transistors over Silicon substrates can be utilized. Control of nanowire LEDs with nanowire transistors will significantly lower the cost, increase the efficiency, improve the manufacturing yield and simplify the structure of the small displays that are used in portable devices. The steps to grow nanowires on Silicon substrates are described. The vertical n-type and p-type nanowire transistors with surrounding gate structures are characterized. While biased at 0.5 V, nanowire transistors with minimum radius or channel width have an OFF current which is less than 1pA, an ON current more than 1 ${\mu}A$, a total delay less than 10 ps and a transconductance gain of more than 10 ${\mu}A/V$. The low power and fast switching characteristics of the nanowire transistor make them an ideal choice for the realization of future displays of portable devices with long battery lifetime.

New Dynamic Logic Gate Design Method for Improved TFT Circuit Performance

  • Jeong, Ju-Young;Kim, Jae-Geun
    • Journal of Information Display
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    • 제6권1호
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    • pp.17-21
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    • 2005
  • We explored a new way of designing dynamic logic gates with low temperature polysilicon thin film transistors to increase the speed. The proposed architecture of logic gates utilizes the structural advantage of smaller junction capacitance of thin film transistors. This method effectively blocks leakage of current through the thin film transistors. Furthermore, the number of transistors used in logic gates is reduced thereby reducing power consumption and chip area. Through HSPICE .simulation, it is confirmed that the circuit speed is also improved in all logic gates designed.

방사선빔 조사를 이용한 질화갈륨 기반 트랜지스터의 내방사선 특성 연구 (Radiation Hardness Evaluation of GaN-based Transistors by Particle-beam Irradiation)

  • 금동민;김형탁
    • 전기학회논문지
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    • 제66권9호
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    • pp.1351-1358
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    • 2017
  • In this work, we investigated radiation hardness of GaN-based transistors which are strong candidates for next-generation power electronics. Field effect transistors with three types of gate structures including metal Schottky gate, recessed gate, and p-AlGaN layer gate were fabricated on AlGaN/GaN heterostructure on Si substrate. The devices were irradiated with energetic protons and alpha-particles. The irradiated transistors exhibited the reduction of on-current and the shift of threshold voltage which were attributed to displacement damage by incident energetic particles at high fluence. However, FET operation was still maintained and leakage characteristics were not degraded, suggesting that GaN-based FETs possess high potential for radiation-hardened electronics.

FinFET SRAM Cells with Asymmetrical Bitline Access Transistors for Enhanced Read Stability

  • Salahuddin, Shairfe Muhammad;Kursun, Volkan;Jiao, Hailong
    • Transactions on Electrical and Electronic Materials
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    • 제16권6호
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    • pp.293-302
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    • 2015
  • Degraded data stability, weaker write ability, and increased leakage power consumption are the primary concerns in scaled static random-access memory (SRAM) circuits. Two new SRAM cells are proposed in this paper for achieving enhanced read data stability and lower leakage power consumption in memory circuits. The bitline access transistors are asymmetrically gate-underlapped in the proposed SRAM cells. The strengths of the asymmetric bitline access transistors are weakened during read operations and enhanced during write operations, as the direction of current flow is reversed. With the proposed hybrid asymmetric SRAM cells, the read data stability is enhanced by up to 71.6% and leakage power consumption is suppressed up to 15.5%, while displaying similar write voltage margin and maintaining identical silicon area as compared to the conventional memory cells in a 15 nm FinFET technology.