• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.1
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• pp.105-110
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• 1999

This paper describes the inverter driven air-condetioner with power factor correction (PFC) circuit. By adopting PFC in the rectifier, we can reduce harmonic injection into power line, improve the efficiency and lower the total system cost compared to conventional inverter only. Also, system performance is improved by stabilizing the output voltage of PFC. In this paper, detailed design procedures for PFC are given, and the several merits with PFC are verified through the simulation and experiment.

• Journal of Power Electronics
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• v.9 no.6
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• pp.903-910
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• 2009

In this paper, a digital average current mode control using diode current sensing technique is proposed. Although the conventional inductor current sensing technique is widely used, the sensed signal of the current is negative. As a result, it requires an additional circuit to be applied to general digital controller ICs. The proposed diode current sensing method not only minimizes the peripheral circuit around the digital IC but also consumes less power to sense current information than the inductor current sensing method. The feasibility of the proposed technique is verified by experiments using a 500W power factor correction (PFC) boost rectifier.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.787-790
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• 2004

In this paper, a novel control scheme compensating for source voltage unbalance and current harmonics and power factor correction in unified active power filter systems combined with shunt passive filters is proposed, where no low/high-pass filter are used in deriving the reference voltage for compensation. Using digital all-pass filters, the phase angle and the reference voltages compensating for harmonic current and unbalanced voltage are derived from the positive sequence component of the unbalanced voltage. The amplitude of d-axis current in a series filter is controlled as zero for power factor correction. The validity of the proposed control scheme has been verified by experimental results.

• Journal of Power Electronics
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• v.12 no.5
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• pp.708-714
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• 2012

This paper presents a new interleaved pulse-width modulation (PWM) boost-flyback converter to achieve power factor correction (PFC) and regulate DC bus voltage. The adopted boost-flyback converter has a high voltage conversion ratio to overcome the limit of conventional boost or buck-boost converter with narrow turn-off period. The proposed converter has wide turn-off period compared with a conventional boost converter. Thus, the higher output voltage can be achieved in the proposed converter. The interleaved PWM can further reduce the input and output ripple currents such that the sizes of inductor and capacitor are reduced. Since boundary conduction mode (BCM) is adopted to achieve power factor correction, power switches are turned on at zero current switching (ZCS) and switching losses are reduced. The circuit configuration, principle operation, system analysis, and design consideration of the proposed converter are presented in detail. Finally, experiments conducted on a laboratory prototype rated at 500W were presented to verify the effectiveness of the converter.

• Proceedings of the KIEE Conference
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• 2005.07c
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• pp.1954-1956
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• 2005

본 논문에서는 SMPS(Switch-Mode Power Supply)의 역률을 개선할 수 있는 power factor correction(PFC) IC를 설계하였다. 설계된 PFC IC에는 전원장치의 power MOSFET을 구동할 수 있는 기능 이외에도 과전압, 과전류 및 단락보호 기능이 포함되어 있다. 또한 시스템이 대기상태에 있는 경우, 전압 및 전류 feedback 제어에 의해 효과적으로 대기전력을 절감할 수 있도록 설계하였다. 설계된 PFC IC는 시스템이 대기상태에서 일정시간동안 부하변동이 없을 경우 이를 감지하여 자동으로 시스템을 off 시켜 대기전력 소모를 최소화 하는 기능을 포함하고 있다.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.8
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• pp.12-17
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• 2008

Most power system loads and delivery apparatus are inductive in nature and therefore operate at a lagging power factor. Applying capacitor banks to a customer will result in a power factor correction and other benefits such as VAR support, increased voltage, reduced power losses, and reduced billing charges. Also there can be power quality problems as a result of adding capacitor banks. The most common are harmonics. This paper provides an in depth analysis on the power factor correction and harmonics reduction of capacitor bank installed at a customer. The EDSA program was used as a simulation tool for the case study.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.55 no.5
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• pp.258-264
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• 2006

This paper presents an integrative control scheme for series-type active power filters combined with shunt passive filters not only to compensate for the source voltage unbalance and current harmonics but also to correct the power factor. To reduce the power capacity of the active filters, passive filters are connected in parallel. Diode rectifiers are replaced by the PWM converters in order to feed the real power back to the source. Power factor control is performed by changing the phase of the load voltage so that the phase of the source current coincides with that of the source voltage. The resultant voltage reference is the addition of the voltage component compensating for the source voltage unbalance and harmonic currents and the voltage component correcting the power factor. The validity of the proposed algorithm has been verified by experimental results.

• Proceedings of the KIEE Conference
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• 1996.07a
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• pp.348-350
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• 1996

A new reset winding clamped forward converter with transformer voltage feedback technique for power factor correction with a single-switch/single-stage is proposed. The proposed converter gives the good power factor correction, low current harmonic distortions, and tight output voltage regulation. The prototype shows the IEC555-2 requirements are met satisfactorily with nearly unity power factor.

• Journal of Power Electronics
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• v.15 no.2
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• pp.356-365
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• 2015

This paper presents a new single phase front-end ac-dc bridgeless power factor correction (PFC) rectifier topology. The proposed converter achieves a high efficiency over a wide range of input and output voltages, a high power factor, low line current harmonics and both step up and step down voltage conversions. This topology is based on a non-inverting buck-boost (Zeta) converter. In this approach, the input diode bridge is removed and a maximum of one diode conducts in a complete switching period. This reduces the conduction losses and the thermal stresses on the switches when compare to existing PFC topologies. Inherent power factor correction is achieved by operating the converter in the discontinuous conduction mode (DCM) which leads to a simplified control circuit. The characteristics of the proposed design, principles of operation, steady state operation analysis, and control structure are described in this paper. An experimental prototype has been built to demonstrate the feasibility of the new converter. Simulation and experimental results are provided to verify the improved power quality at the AC mains and the lower conduction losses of the converter.

• Journal of Power Electronics
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• v.6 no.4
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• pp.330-339
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• 2006

This paper deals with novel electronic ballast based on single-stage power processing topology using a symmetrical half-bridge inverter and current injection circuit. The half-bridge inverter drives the output parallel resonant circuit and injects current through the power factor correction (PFC) circuit. Because of high frequency current injection and high frequency modulated voltage, the proposed circuit maintains the unity power factor (UPF) with low THD even under wide variation in ac input voltage. This circuit needs minimum and lower sized components to achieve the UPF and high efficiency. This leads to an increase in reliability of ballast at low cost. Furthermore, to reduce cost, the electronic ballast is designed for two series-connected fluorescent lamps (FL). The analysis and experimental results are presented for ($2{\times}36$ Watt) fluorescent lamps operating at 50 kHz switching frequency and input line voltage (230 V, 50 Hz).