• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.266-269
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• 1999

Several power factor correction(PFC) circuits are presented to achieve high PF electronic ballast for both voltage-fed and current-fed electronic ballast. The proposed PFC circuits use valley-fill(VF) type DC-link stages modified from the conventional VF circuit to adopt the charge pumping method for PFC operations during the valley intervals. In voltage-fed ballast, charge pump capacitors are connected with the resonant capacitors. In current-fed type, the charge pump capacitors are connected with the additional secondary-side of the power transformer. The measured PF and THD are higher than 0.99 and 15% for all proposed PFC circuits. The lamp current CF is also acceptable in the proposed circuits. The proposed circuit is suitable for implementing cost-effective electronic ballast.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.997-1000
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• 2000

The purpose of this paper is to verify the appropriation of power electronics circuit by applying the most powerful and widely used simulator PSPICE and SIMULINK for adapted variable control technics. Power electronics librarys modeled and adapted to circuit. It is proved that simulation and excute are almost same.

• Proceedings of the KIEE Conference
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• 1999.11a
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• pp.7-9
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• 1999

Power semiconductor macro modeled by SIMULINK such as diode, thyristor. Loads are modeled by SIMULINK and PSPICE through their algorithms. For proved these modeling accurate, simulation techniques which are generally used in the field of power electronics circuits are adapted in power electronics and systems.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.1063-1064
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• 2008

In this paper, two kinds of the protection circuits are proposed and simulated to verify their performances. One is an over current protection circuit, and the other is a no load protection circuit which reduces power consumption. These protection circuits of an LED drive circuit can reduce power consumption and prevent to damage the elements.

• Journal of Power Electronics
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• v.11 no.1
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• pp.1-9
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• 2011

This paper describes a two quadrant bidirectional soft switching converter for ultra capacitor interface circuits. The total efficiency of the energy storage system in terms of size and cost can be increased by a combination of batteries and ultra capacitors. The required system energy is provided by a battery, while an ultra capacitor is used at high load power pulses. The ultra capacitor voltage changes during charge and discharge modes, therefore an interface circuit is required between the ultra capacitor and the battery. This interface circuit must have good efficiency while providing bidirectional power conversion to capture energy from regenerative braking, downhill driving and the protecting ultra capacitor from immediate discharge. In this paper a fully soft switched two quadrant bidirectional soft switching converter for ultra capacitor interface circuits is introduced and the elements of the converter are reduced considerably. In this paper, zero voltage transient (ZVT) and zero current transient (ZCT) techniques are applied to increase efficiency. The proposed converter acts as a ZCT Buck to charge the ultra capacitor. On the other hand, it acts as a ZVT Boost to discharge the ultra capacitor. A laboratory prototype converter is designed and realized for hybrid vehicle applications. The experimental results presented confirm the theoretical and simulation results.

• Journal of Power Electronics
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• v.12 no.6
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• pp.878-885
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• 2012

A new sustainer with primary-side integration of DC/DC converters and energy recovery(SPIDER) circuits is proposed. The proposed circuit operates as a DC-DC converter during address period and energy recovery circuit during sustain period. Therefore, the conventional three electronic circuits composed of the power supply, X-driver, and Y-driver can be reduced to one circuit. As a result, it has desirable advantages such as a simple structure, less mass, fewer devices and cost reduction. Moreover, since the Zero Voltage Switching (ZVS) of all power switches can be guaranteed, a switching loss can be considerably decreased. To confirm the operation, validity, and features of the proposed circuit, experimental results from a prototype for 42-inch PDP are presented.

• ETRI Journal
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• v.24 no.6
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• pp.473-476
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• 2002

This letter proposes an efficient kernel-based partitioning algorithm for reducing area and power dissipation in combinational circuit designs using don't-care sets. The proposed algorithm decreases power dissipation by partitioning a given circuit using a kernel extracted from the logic. The proposed algorithm also reduces the area overhead by minimizing duplicated gates in the partitioned sub-circuits. The partitioned subcircuits are further optimized utilizing observability don't-care sets. Experimental results for the MCNC benchmarks show that the proposed algorithm synthesizes circuits that on the average consume 22.5% less power and have 12.7% less area than circuits generated by previous algorithms based on a precomputation scheme.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.257-263
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• 2006

New charge pump circuits with low area and high power efficiency are proposed and verified in this paper. These pump circuits do not suffer the voltage stress higher than $V_{DD}$ across their pumping capacitors. Thus they can use the thin-oxide MOSFETs as the pumping capacitors. Using the thin-oxide capacitors can reduce the area of charge pumps greatly while keeping their driving capability. Comparing the new pump (NCP-2) with the conventional pump circuit using the thick-oxide capacitors shows that the power efficiency of NCP-2 is the same with the conventional one but the area efficiency of NCP-2 is improved as much as 71.8% over the conventional one, when the $V_{PP}/V_{DD}$ ratio is 3.5 and $V_{DD}$=1.8V.

• ETRI Journal
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• v.30 no.3
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• pp.451-460
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• 2008

Recently, the power consumption of integrated circuits has been attracting increasing attention. Many techniques have been studied to improve the power efficiency of digital signal processing units such as fast Fourier transform (FFT) processors, which are popularly employed in both traditional research fields, such as satellite communications, and thriving consumer electronics, such as wireless communications. This paper presents solutions based on parallel architectures for high throughput and power efficient FFT cores. Different combinations of hybrid low-power techniques are exploited to reduce power consumption, such as multiplierless units which replace the complex multipliers in FFTs, low-power commutators based on an advanced interconnection, and parallel-pipelined architectures. A number of FFT cores are implemented and evaluated for their power/area performance. The results show that up to 38% and 55% power savings can be achieved by the proposed pipelined FFTs and parallel-pipelined FFTs respectively, compared to the conventional pipelined FFT processor architectures.

• Journal of Power Electronics
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• v.12 no.6
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• pp.954-959
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• 2012

A hybrid switch that uses a microelectromechanical system (MEMS) switch as a gate driver of a MOSFET is applied to an energy harvesting system. The power management circuit adopting the hybrid switch provides ultralow leakage, self-referencing, and high current handling capability. Measurements show that solar energy harvester circuit utilizing the MEMS-MOSFET hybrid switch accumulates energy and charges a battery or drive a resistive load without any constant power supply and reference voltage. The leakage current during energy accumulation is less than 10 pA. The power management circuit adopting the proposed hybrid switch is believed to be an ideal solution to self-powered wireless sensor nodes in smart grid systems.