• Proceedings of the Korean Information Science Society Conference
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• 2003.04d
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• pp.253-255
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• 2003

Electricity is the prime commodity in mobile device, e.g. smart phone, PDA, MP3 player and etc. This strict restriction on power consumption requirement of the mobile device puts unique demand in designing hardware and software components of the device. In this paper, we address the issue of minimizing the power consumption in retrieving the continuous media data from the disk drive for real-time playback purpose. Different from the legacy text based data, real-time multimedia playback requires that the storage supplies the data block continuous fashion. This may put immense burden on the power scarce environment since the disk Is required to be active for the entire playback duration. We develop elaborate algorithm which carefully analyzes the power consumption profile of the disk drive and which establishes the data retrieval schedule for the given playback. It computes the amount of data blocks to read, the length of active and standby period. According to our simulation result, the ARM algorithm exhibits superior performance in continuous media retrieval from the aspect of power consumption to legacy playback scheme.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.886-889
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• 2010

Power consumption measurement in sensor network is difficult to proceed by survey in real field. Thus, through simulation, the power consumption is estimated and replacement time of nodes are decided. A simulation tool simulates various facts such as power consumption, packet transmission traffic, network topology and etc. In this paper, it suggests sensor node power model to simulate power consumption which has large importance among simulation facts in sensor network. This model omits calculating expressions that the data originally surveyed can substitute with, according to power consumption property of each functions in sensor node in order to minimize calculations in simulation. In this case accuracy of power consumption estimation will be reduced, but can simulate it faster due to reduced calculation. Suggested model is fitted to analyze power consumption difference between two or more sensor network algorithms with rapid simulation speed rather than accurate simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.5
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• pp.963-970
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• 2008

Recently, several papers for reading meters remotely using RFID/USN technologies have been presented. In the case of water meter, there has been neither commercial product nor paper. In this paper, we describe the design and implementation of wireless digital water meter with low power consumption. We use magnetic hole sensors to compute the amount of water consumption. The meter of water consumption is transferred via ZigBee wireless protocol to a gateway. Low power consumption design is essential since a battery should last till the life time of water meter. We present that dual batteries haying 3V, 3000mAh, would last 8 years by analyzing the real power consumption of our water meter.

• Journal of the Korea Society of Computer and Information
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• v.20 no.7
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• pp.57-64
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• 2015

In this paper, we propose a design of microwave motion detector using X-band doppler radar sensor to minimize the power consumption. To minimize the power consumption and implement battery operated system, pulse input with 2 KHz, 4% duty cycle is exerted on the doppler radar sensor. In order to simplify the process of working with ATmega2560 microcontroller unit, Arduino compatible board is designed and implemented. Arduino is open source hardware and many library software is published as open source tools. Smartphone app is also proposed and designed as a real-time user interface of the motion detector. The SQLite database on the Android mobile operating system is used for recording raw data of motion detection for post-processing job, such as fast Fourier transform (FFT). Bluetooth interface module is implemented on the motion detection board as a wireless communication interface to the smartphone. The speed of human movement is identified by post-processing FFT.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.4
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• pp.603-610
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• 2021

In this paper, we extract the user's power consumption patterns, and model the optimal consumption patterns by applying the user's environment and emotion. Based on the comparative analysis of these two patterns, we present an efficient power consumption method through changes in the user's power consumption behavior. To extract significant consumption patterns, vector standardization and binary data transformation methods are used, and learning about the ensemble's ensemble with k-means clustering is applied, and applying the support factor according to the value of k. The optimal power consumption pattern model is generated by applying forced and emotion-based control based on the learning results for ensemble aggregates with relatively low average consumption. Through experiments, we validate that it can be applied to a variety of windows through the number or size adjustment of clusters to enable forced and emotion-based control according to the user's intentions by identifying the correlation between the number of clusters and the consistency ratios.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.11C
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• pp.1132-1138
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• 2002

This paper proposes a reducing power consumption of a scheduling algorithm for optimal selection of supply voltage. In scheduling of reduction power consumption, we determine the control steps of operations to be executed by exploiting the possibility of using variable voltage levels to reduce power consumption. In the optimal selection of supply voltage binding, we minimize the main factor of the power consumption of the switching activity on the registers using a graph coloring technique. From a set of experiments using high-level benchmark examples, we show that the proposed algorithm prefer to use optimal selection supply voltages rather than uniformed single voltage is effective in reducing power consumption.

• Journal of Korea Society of Digital Industry and Information Management
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• v.10 no.1
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• pp.1-6
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• 2014

In this paper, we propose a CPLD low power algorithm considering the structure. The proposed algorithm is implemented CPLD circuit FC(Feasible Cluster) for generating a problem occurs when the node being split to overcome the area and power consumption can reduce the algorithm. CPLD to configure and limitations of the LE is that the number of OR-terms. FC consists of an OR node is divided into mainly as a way to reduce the power consumption with the highest number of output nodes is divided into a top priority. The highest number of output nodes with the highest number of switching nodes become a cut-point. Division of the node is the number of OR-terms of the number of OR-terms LE is greater than adding the input and output of the inverter converts the AND. Reduce the level, power consumption and area. The proposed algorithm to MCNC logic circuits by applying a synthetic benchmark experimental results of 13% compared to the number of logical blocks decreased. 8% of the power consumption results in a reduced efficiency of the algorithm represented been demonstrated.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.10 no.1
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• pp.33-39
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• 2011

This paper considers a performance analysis of set-top box (STB) power saving schemes. STB converts the signal into content which is then displayed on the television (TV) screen, and there are typically two operation modes: on mode and stand-by mode. The total energy consumption (TEC), a typical measure of power consumption of STB, is defined by the sum of power consumption in each mode. Recently there are some works of STB power saving schemes that transit STB operation modes efficiently, and the mode transition time point of those schemes can be different. Thus it is required to develop a performance evaluation method that reflects mode transition time points of each scheme to get TEC correctly. This paper proposes a performance evaluation method for STB power consumption using Poisson process to consider the mode transition time point. By modeling STB mode transitions as events of Poisson process, the average time duration of STB mode is computed and accordingly the effect of power saving is evaluated. The performance evaluation result shows that the proposed method achieves 1 to 19% improvement in power consumption compared with a conventional performance evaluation method.

• Journal of the Korea Society of Computer and Information
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• v.19 no.4
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• pp.25-33
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• 2014

This paper proposes a power-efficient scheduling scheme that stochastically minimizes the power consumption of real-time tasks while meeting their deadlines on multicore processors. In the proposed scheme, uncertain computation amounts of given tasks are translated into probabilistic computation amounts based on their past completion amounts, and the mean power consumption of the translated probabilistic computation amounts is minimized with a finite set of discrete clock frequencies. Also, when system load is low, the proposed scheme activates a part of all available cores with unused cores powered off, considering the leakage power consumption of cores. Evaluation shows that the scheme saves up to 69% power consumption of the previous method.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.3
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• pp.183-188
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• 2015

A 10-bit 10MS/s low power consumption successive approximation register (SAR) analog-to-digital converter (ADC) using a straightforward capacitive digital-to-analog converter (DAC) is presented in this paper. In the proposed capacitive DAC, switching is always straightforward, and its value is half of the peak-to-peak voltage in each step. Also the most significant bit (MSB) is decided without any switching power consumption. The application of the straightforward switching causes lower power consumption in the structure. The input is sampled at the bottom plate of the capacitor digital-to-analog converter (CDAC) as it provides better linearity and a higher effective number of bits. The comparator applies adaptive power control, which reduces the overall power consumption. The differential prototype SAR ADC was implemented with $0.18{\mu}m$ complementary metal-oxide semiconductor (CMOS) technology and achieves an effective number of bits (ENOB) of 9.49 at a sampling frequency of 10MS/s. The structure consumes 0.522mW from a 1.8V supply. Signal to noise-plus-distortion ratio (SNDR) and spurious free dynamic range (SFDR) are 59.5 dB and 67.1 dB and the figure of merit (FOM) is 95 fJ/conversion-step.