Reducing Power Consumption of a Scheduling Algorithm for Optimal Selection of Supply Voltage under the Time Constraint |
최지영
(제천기능대학 정보통신설비과)
김희석 (청주대학교 전자공학과) |
1 |
Estimation of Average Switching Activity in Combination and Sequential Circuits
/
|
2 |
Minimizing Power Consumption in Digital CMOS Circuits
/
ScienceOn |
3 |
Behavioral to Structural Translation in a Bit-Serial Silicon Compiler
/
|
4 |
Power-Profiler : Optimizing ASICs Power Consumption at the Behavioral Level
/
|
5 |
Minimizing power consumption in digital CMOS circuit
/
ScienceOn |
6 |
Behavioral synthesis for low power
/
|
7 |
Energy minimization using mutiple supply voltage
/
|
8 |
Datapath scheduling with multipe supply voltages and level converters
/
|
9 |
High-level synthesis techiques for reducing the activity of functional unit
/
|
10 |
Low-Power CMOS Digital Design
/
ScienceOn |
11 |
HYPER-LP: A System fo Power Minimization Using Architecture Transformation
/
|
12 |
Optimizing power using transformations
/
ScienceOn |
13 |
Power Estimation of High-Level Synthesis
/
|
14 |
Register Allocation and Binding for Low Power
/
|
15 |
Simultaneous scheduling binding for low power minimization during microarchitecture synthesis
/
|
16 |
A Design Methodology for Behavioral Level Power Exploration : Implementation and Experiments
/
|