• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.4
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• pp.64-69
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• 2009

This paper addresses the simulation methodology of signal integrity and power integrity for mobile display modules. The proposed technique can be applied to analyse a circuit module which consist of connector, FPCB and driver ICs. The recent demand of serial interconnection technology in the mobile display industry needs delicate impedance control of signal and power traces to prohibit system malfunctioning and to reduce electromagnetic field radiation. Based on the S-parameter and Z-parameter analysis, we analyse the correlation between frequency-domain and time-domain measurements. With multi-port macros, signal integrity can be included in power integrity analysis in time domain.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.48 no.1
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• pp.63-72
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• 2020

As the design complexity and performances are increased in satellite electronic board, noise related problems are also increased. To minimize the noise issues, various design improvements are performed by power integrity and signal integrity analysis in this research. Static power and dynamic power design are reviewed and improved by DC IR drop and power impedance analysis. Signal integrity design is reviewed and improved by time domain signal wave analysis and PCB(Printed Circuit Board) design modifications. And also power planes resonance modes are checked and mitigation measures are verified by simulation. Finally, it is checked that radiated noise is reduced after design improvements by EMC(Electro Magnetic Compatibility) RE(Radiated Emission) measurement results.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.3-14
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• 2013

In this paper, key design issues and considerations for Signal Integrity(SI) and Power Integrity(PI) of a TSV-based 3D IC are introduced. For the signal integrity and power integrity of a TSV-based 3-D IC channel, analytical modeling and analysis results of a TSV-based 3-D channel and power delivery network (PDN) are presented. In addition, various design techniques and solutions which are to improve the electrical performance of a 3-D IC are investigated.

• 한국ITS학회:학술대회논문집
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• 2008.11a
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• pp.391-394
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• 2008

• ETRI Journal
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• v.41 no.5
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• pp.670-683
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• 2019

In this paper, we analyzed the signal integrity of a system interconnection module for a proposed high-density server. The proposed server integrates several components into a chassis. Therefore, the proposed server can access multiple computing resources. To support the system interconnection, among the highly integrated computing resources, the interconnection module, which is based on Serial RapidIO, has been newly adopted and supports a bandwidth of 800 Gbps while routing 160 differential signal traces. The module was designed for two different stack-up types on a printed circuit board. Each module was designed into 12- (version 1) and 14-layer (version 2) versions with thicknesses of 1.5T and 1.8T, respectively. Version 1 has a structure with two consecutive high-speed signal-layers in the middle of two power planes, whereas Version 2 has a single high-speed signal placed only in the space between two power planes. To analyze the signal integrity of the module, we probed the S-parameters, eye-diagrams, and crosstalk voltages. The results show that the high-speed signal integrity of Version 2 has a better quality than Version 1, even if the signal trace length is increased.

• Journal of electromagnetic engineering and science
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• v.5 no.4
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• pp.193-196
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• 2005

The DC power-bus for the PCB is loaded with metal walls on its selected sides and is characterized electromagnetically. This is a novel concept of approach to mitigate the spurious resonance and finally signal integrity problems. In particular, the peak at DC, which is always in the way to secure parallel-plates' EMC, can be completely removed by the proposed method. Through the findings of this study, the effect of metal-loading of the power-bus will be presented along with the impression that the suggested technique can tackle the headaches of signal integrity, ground bounce, EMIs.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.35-50
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• 2013

This paper discusses effects of mesh planes on signal integrity in high-speed glass ceramic packages. One of serious signal integrity issues in high-speed glass ceramic packages is high far-end (FE) noise coupling between signal interconnects. Based on signal integrity analysis, a methodology is presented for reducing far-end noise coupling between signal interconnects in high-speed glass ceramic modules. This methodology employing power/ground mesh planes with alternating spacing and a via-connected coplanar-type shield (VCS) structure is suggested to minimize far-end noise coupling between signal lines in high-speed glass ceramic packages. Optimized interconnect structure based on this methodology has demonstrated that the saturated far-end noise coupling of a typical interconnect structure in glass ceramic modules could be reduced significantly by 73.3 %.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.6
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• pp.452-460
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• 2021

As the global electric vehicle (EV) market expands, eco-friendly EV that complement performance and safety problems continue to be released and the market is growing. However, in the case of EVs, the inconvenience of charging, safety problems such as electric shock, and electromagnetic interference (EMI) problems caused by the interlocking of various electronic components are problems that must be solved in EVs. The use of wireless power transmission technology can solve the problem of safety by not dealing with high current and high voltage directly and solving the inconvenience of charging EVs. In this paper, in order to reduce EMI a wireless charging control module, which is a key electronic component of WPT of EV. EMI reduction was designed through simulation of problems such as resonance and impedance that may occur in the power supply and signal distortion between high-speed communication that may occur in the signal part. Therefore, through the EMI reduction design with power integrity and signal integrity, the WPT wireless charging control module for electric vehicles reduces 10 dBu V/m and 15 dBu V/m, respectively, in 800 MHz to 1 GHz bands and 1.5 GHz bnad.

• Journal of international Conference on Electrical Machines and Systems
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• v.3 no.3
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• pp.248-251
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• 2014

As more vehicles become equipped with advanced electronic control systems, more consideration is needed with regards to automotive safety issues related to the effects of electromagnetic waves. Unwanted electromagnetic waves from the antenna, electricity and other electronic devices cause the performance and safety problem of automotive components. In general, Power Integrity and Signal Integrity analysis have been widely used, but these analyses have stayed PCB level. PCB base analysis is different from radiated emission TEST condition so its results are used just for reference. This paper proposes EMC optimization technology using module level 3-dimensional radiation simulation process closed to fundamental test conditions. If module level EMC analysis, which is proposed in this study, is applied to all automotive electronics systems, unexpected EMC noise will be prevented.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.51-57
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• 2013

The current expanding mobile markets incessantly demands small form factor, low power consumption and high aggregate throughput for silicon-level integration such as memory to logic system. One of emerging solution for meeting this high market demand is 3D through silicon stacking (TSS) technology. Main challenges to bring 3D TSS technology to the volume production level are establishing a cost effective supply chain and building a reliable manufacturing processes. In addition, this technology inherently help increase number of IOs and shorten interconnect length. With those benefits, however, potential signal and power integrity risks are also elevated; increase in PDN inductance, channel loss on substrate, crosstalk and parasitic capacitance. This paper will report recent progress of wide IO memory to high count TSV logic device assembly development work. 28 nm node TSV test vehicles were fabricated by the foundry and assembled. Successful integration of memory wide IO chip with less than a millimeter package thickness form factor was achieved. For this successful integration, we discussed potential signal and power integrity challenges. This report demonstrated functional wide IO memory to 28 nm logic device assembly using 3D package architecture with such a thin form factor.