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http://dx.doi.org/10.4218/etrij.2018-0021

Signal integrity analysis of system interconnection module of high-density server supporting serial RapidIO  

Kwon, Hyukje (SW and Contents Research Laboratory, Electronics and Telecommunications Research Institute)
Kwon, Wonok (SW and Contents Research Laboratory, Electronics and Telecommunications Research Institute)
Oh, Myeong-Hoon (SW and Contents Research Laboratory, Electronics and Telecommunications Research Institute)
Kim, Hagyoung (SW and Contents Research Laboratory, Electronics and Telecommunications Research Institute)
Publication Information
ETRI Journal / v.41, no.5, 2019 , pp. 670-683 More about this Journal
Abstract
In this paper, we analyzed the signal integrity of a system interconnection module for a proposed high-density server. The proposed server integrates several components into a chassis. Therefore, the proposed server can access multiple computing resources. To support the system interconnection, among the highly integrated computing resources, the interconnection module, which is based on Serial RapidIO, has been newly adopted and supports a bandwidth of 800 Gbps while routing 160 differential signal traces. The module was designed for two different stack-up types on a printed circuit board. Each module was designed into 12- (version 1) and 14-layer (version 2) versions with thicknesses of 1.5T and 1.8T, respectively. Version 1 has a structure with two consecutive high-speed signal-layers in the middle of two power planes, whereas Version 2 has a single high-speed signal placed only in the space between two power planes. To analyze the signal integrity of the module, we probed the S-parameters, eye-diagrams, and crosstalk voltages. The results show that the high-speed signal integrity of Version 2 has a better quality than Version 1, even if the signal trace length is increased.
Keywords
crosstalk; high-density server; PCB stack-up; serial RapidIO; system interconnection;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
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1 M. H. Oh et al., Wire optimization and delay reduction for highperformance on-chip interconnection in GALS systems, ETRI J. 39 (2017), 582-591.   DOI
2 J. Zhang et al. A hybrid stack-up of printed circuit board for high-speed networking systems, in IEEE Int. Symp. Electromagn. Compat., Pittsburgh, PA, USA, Aug. 6-10, 2012, pp. 554-559.
3 A. R. Chada et al. Estimation of mode conversion and crosstalk impact from a single-ended aggressor to a differential victim using statistical BER analysis, in IEEE 64th Electron. Compon. Technol. Conf. (ECTC), Orlando, FL, USA, May 27-30, 2014, pp. 2081-2087.
4 I. Kim et al. Design optimization of board-level signal integrity depending on PCB stack-up configuration in a mobile device, in Asia-Pacific Int. Symp. Electromagn. Compat. (APEMC), Seoul, Rep. of Korea, June 20-23, 2017, pp. 334-336.
5 K. Xiao et al. Inter-layer Crosstalk Management in Differential Dual-striplines, in IEEE Int. Symp. Electromagn. Compat., Denver, CO, USA, Aug. 5-9, 2013, pp. 724-729.
6 C. L. Liao et al., PCB stack-up design and optimization for next generation speeds, in IEEE Conf. Elect. Performance Electron. Packaging Syst. (EPEPS), San Diego, CA, USA, Oct. 23-26, 2016, pp. 155-158.
7 M. Kim, Multi-stack technique for a compact and wideband EBG structure in high-speed multilayer printed circuit boards, ETRI J. 38 (2016), 903-910.   DOI
8 Cisco public, Cisco Visual Networking Index: Forecast and Methodology, 2016-2021, White Paper, June 6, 2017.
9 K. K. Patel and S. M. Patel, Internet of things-IOT: definition, characteristics, architecture, enabling technologies, application & future challenges, Int. J. Eng. Sci. Comput. 6 (2016), 6122-6131.
10 Intel Server Platforms Micro Server Technology, Flexible Scaleout with lightweight Micro Servers White paper, Apr. 2011.
11 RapidIO Interconnect Specification, Rev. 2.1, RapidO Organization, Aug. 2009
12 M. Marazakis et al., EUROSERVER: Share-Anything Scale-Out Micro-Server Design, in Des., Autom. Test Eur. Conf. Exhibition (DATE), Dresden, Germany, Mar. 14-18, 2016, pp. 673-683.
13 N. Heath, Microservers: What you need to know, 2014. Accessed http://www.zdnet.com/article/microservers-what-you-need-to-know.
14 Global Data Center Microserver Market 2016-2020, Infiniti Research Limited, 2016
15 D. Paul, RapidIO for Low Latency servers and wireless base station, 2013, Accessed www.rapidio.org/files/IDT_RapidIO_ Tour_As ia_2013.pdf.
16 M. Eargham, Computer architecture, Prentice Hall, Upper Saddle River, NJ, USA, 1996.
17 D. A. Reed and D. C. Grunwald, The performance of multicomputer interconnection networks, Comput. 20 (1987), 63-73.
18 L. N. Bhuyan, Interconnection networks for parallel and distributed processing, Comput. 20 (1987), 9-12.   DOI
19 Gabriele Kotsis, Interconnection Topologies and Routing for Parallel Processing Systems, Technical Report Series, 1992.
20 M. Alam and A. K. Varshney, A comparative study of interconnection network, Int. J. Comput. Applicat. 127 (2015), 37-43.
21 N. Adhikari and C. R. Tripathy, The folded crossed cube: A new interconnection network for parallel systems, Int. J. Comput. Applicat. 4 (2010), 43-50.
22 D. Froelich. PCIe CEM 4.0 Previews, in PCI-SIG Developers Conf., Santa Clara, CA, USA, June 7-8, 2017.
23 C. R. Tripathy and N. Adhikari, On a new multicomputer interconnect topology for massively parallel systems, Int. J. Distrib. Parallel Syst. 2 (2011), 162-180.
24 A. El-Amawy and S. Latifi, Properties and performance of Folded Hypercubes, IEEE Trans. Parallel Distrib. Syst. 2 (1991), 31-42.   DOI
25 J. Xiaosong and Z. Runjing. Crosstalk analysis and simulation in high-speed PCB design, in Int. Conf. Electron. Meas. Instrum., Xi'an, China, Aug. 16-18, 2007, pp. 2:427-440.
26 H. W. Johnson and M. Graham, High-speed Digital Design, A handbook of Black Magic, Prentice Hall, Englewood Cliffs, NJ, USA, 1993.
27 P. V. Reddy, S. Jena, and V. K. Prasad, Reliability of Folded Hypercube, in Int. Conf. Parallel, Distrib. Grid Comput., Waknaghat, India, Dec. 22-24, 2016, pp. 381-385.