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Effects of Mesh Planes on Signal Integrity in Glass Ceramic Packages for High-Performance Servers  

Choi, Jinwoo (IBM)
Altabella Lazzi, Dulce M. (IBM)
Becker, Wiren D. (IBM)
Publication Information
The Proceeding of the Korean Institute of Electromagnetic Engineering and Science / v.24, no.2, 2013 , pp. 35-50 More about this Journal
Abstract
This paper discusses effects of mesh planes on signal integrity in high-speed glass ceramic packages. One of serious signal integrity issues in high-speed glass ceramic packages is high far-end (FE) noise coupling between signal interconnects. Based on signal integrity analysis, a methodology is presented for reducing far-end noise coupling between signal interconnects in high-speed glass ceramic modules. This methodology employing power/ground mesh planes with alternating spacing and a via-connected coplanar-type shield (VCS) structure is suggested to minimize far-end noise coupling between signal lines in high-speed glass ceramic packages. Optimized interconnect structure based on this methodology has demonstrated that the saturated far-end noise coupling of a typical interconnect structure in glass ceramic modules could be reduced significantly by 73.3 %.
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1 J. Choi, S. Min, J. Kim, M. Swaminathan, W. Beyene, and C. Yuan, "Modeling and analysis of power distribution networks for gigabit applications", IEEE Trans. on Mobile Computing, vol. 2, no. 4, pp. 299-313, Oct.-Dec. 2003.   DOI   ScienceOn
2 R. R. Tummala et al., "Packaging technology for IBM's latest mainframe computers", Proc. EIA /CPMT 41st Electronic Components and Technology Conf, Atlanta, GA, pp. 682-688, May 1991.
3 A. Deutsch, "Electrical characteristics of interconnections for high performance systems", Proc. of the IEEE, vol. 86, no. 2, pp. 335-337, 1998.
4 R. R. Tummala, Rymaszewski, Microelectronics Packaging Handbook, Van Nostrand Reinhold, New York, 1989.
5 J. Choi, R. Weekly, A. Haridass, and T. Zhou, "Methodology for minimizing far-end noise coupling between interconnects in high-speed ceramic modules", IEEE 59th Electronic Components and Technology Conference (ECTC), San Diego, California, pp. 1227-1233, May 2009.
6 J. U. Knickerbocker et al., "An advanced multichip module (MCM) for high-performance UNIX servers", IBM J. Res. & Dev. vol. 46, no. 6, pp. 779-804, Nov. 2002.   DOI
7 A. C. Cangellaris et al., "Electrical characteristics of multichip module interconnects with perforated reference planes", IEEE Trans-CPMT, vol. 16, no. 1, pp. 113-118, 1993.
8 B. J. Rubin, "Comparison of mesh and solid planes for use in electrical packaging", IEEE Proc 5th Topical Meeting on Electrical Performance of Electronic Packaging, pp. 217-219, Oct. 1996.
9 J. Choi, Z. Chen, D. W. Becker, J. Morsey and B. Rubin, "Constructing 3D package component broadband electrical models with correct DC values.", IEEE 20th Topical Meeting of Electrical Performance of Electronic Packaging and Systems (EPEPS), Austin, Texas, pp. 253-256, Oct. 2010.
10 W. T. Weeks, "Calculation of coefficients of capacitance of multiconductor transmission lines in the presence of a dielectric interface", IEEE Trans- MTT, vol. MTT-18, pp. 35-43 ,1970.
11 W. T. Weeks, et al., "Resistive and inductive skin effect in rectangular conductors", IBM J. Res. Develop., vol. 23, no. 6, pp. 652-660, 1979.   DOI
12 A. E. Ruehli et al., "Method for generating an electrical circuit comprising dielectrics", U.S. Patent #6192507, May 1998.
13 B. Rubin et al., "Radiation and scattering from structures involving finite-size dielectric regions", IEEE Trans-Antennas Propagat., vol. 38, pp. 1863-1873, 1990.   DOI   ScienceOn
14 B. Rubin et al., "Calculation of multi-port parameters of electronic packages", IEEE Proc 2nd Topical Meeting on Electrical Performance of Electronic Packaging, pp. 37-39, Oct. 1993.
15 B. Rubin, "The propagation characteristics of signal lines in a mesh-plane environment", IEEE Trans. Microwave Theory and Techniques, vol. MTT-31, no. 5, pp. 522-531, May 1984.
16 J. Choi, B. Krauter, A. Haridass, R. Weekly, D. Douriet, and S. Chun, "Crosstalk analysis between interconnects in high-speed server packages", IEEE 57th Electronic Components and Technology Conference (ECTC), Reno, Nevada, pp. 333-338, May 2007.
17 J. Choi, W. D. Becker, and T. Zhou, "High-speed ceramic modules with hybrid referencing scheme for improved performance and reduced cost", U.S. Patent #8339803, Dec. 2012.
18 B. Young, Digital Signal Integrity: Modeling and Simulation with Interconnects and Packages, Prentice- Hall, New York, pp. 98-104, 2001.
19 E. Bogatin, Signal Integrity-Simplified, Prentice-Hall, New Jersey, pp.401-469, 2004.
20 J. Choi, S. Chun, A. Haridass, and R. Weekly, "Noise coupling reduction and impedance discontinuity control in high speed ceramic modules", U.S. Patent #8288657, Oct. 2012.
21 J. Choi, "Mesh planes with alternating spaces for multi-layered ceramic packages", U.S. Patent Applications # 820110319, Nov. 2011.