• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.80-81
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• 2008

Schottky barrier thin film transistors (SB-TFT) on polycrystalline silicon(poly-Si) are fabricated by platinum silicided source/drain for p-type SB-TFT. High quality poly-Si film were obtained by crystallizing the amorphous Si film with excimer laser annealing (ELA) or solid phase crystallization (SPC) method. The fabricated poly-Si SB-TFTs showed low leakage current level and a large on/off current ratio larger than $10^5$. Significant improvement of electrical characteristics were obtained by the additional forming gas annealing in 2% $H_2/N_2$ ambient, which is attributed to the termination of dangling bond at the poly-Si grain boundaries as well as the reduction of interface trap states at gate oxide/poly-Si channel.

• Korean Journal of Materials Research
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• v.1 no.1
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• pp.23-28
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• 1991

The resistivity of polycrystalline silicon film deposited by low pressure chemical vapor deposition and doped by arsenic Implantation has been investigated as a function of dopant concentration and testing temperature ranging from $25^{\circ}C$ to $105^{\circ}C$ . The resistivity vs. doping concentration curve had a peak point with highest activation energy with respect to the dependence of the resistivity on temperature. We showed that $O_2$ plasma anneal followed by heat-treatment in $N_2$ ambient was able to recover the resistivity degraded by the plasma deposited passivation layers.

• Journal of the Korean Solar Energy Society
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• v.21 no.1
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• pp.1-10
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• 2001

Polycrystalline silicon(poly-Si) films are deposited on low temperature glass substrate by Hot-CVD(HWCVD). The structural properties of the poly-Si films are strongly dependent on the temperature$(T_w)$. The films deposited at high $T_w$ of $2000^{\circ}C$ have superior crystalline proper average lateral grain sizes are larger than $1{\mu}m$ and there are no vertical grain boundaries. The sur of the high $T_w$ samples are naturally textured like pyramid shape. These large grain size and text surface are believed to give high current density when applied to solar cells. However, the poly films are structurally porous and contains high defect density, by which high concentration of C and O resulted within the films by air-penetration after removed from chamber.

• Korean Journal of Metals and Materials
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• v.46 no.3
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• pp.159-168
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• 2008

Thermally-evaporated 10 nm-Ni/1 nm-Ru/(30 nm or 70 nm-poly)Si structures were fabricated in order to investigate the thermal stability of Ru-inserted nickel monosilicide. The silicide samples underwent rapid thermal anne aling at $300{\sim}1,100^{\circ}C$ for 40 seconds. Silicides suitable for the salicide process were formed on the top of the single crystal and polycrystalline silicon substrates mimicking actives and gates. The sheet resistance was measured using a four-point probe. High resolution X-ray diffraction and Auger depth profiling were used for phase and chemical composition analysis, respectively. Transmission electron microscope and scanning probe microscope(SPM) were used to determine the cross-sectional structure and surface roughness. The silicide, which formed on single crystal silicon and 30 nm polysilicon substrate, could defer the transformation of $Ni_2Si $i and $NiSi_2 $, and was stable at temperatures up to $1,100^{\circ}C$ and $1,100^{\circ}C$, respectively. Regarding microstructure, the nano-size NiSi preferred phase was observed on single crystalline Si substrate, and agglomerate phase was shown on 30 nm-thick polycrystalline Si substrate, respectively. The silicide, formed on 70 nm polysilicon substrate, showed high resistance at temperatures >$700^{\circ}C$ caused by mixed microstructure. Through SPM analysis, we confirmed that the surface roughness increased abruptly on single crystal Si substrate while not changed on polycrystalline substrate. The Ru-inserted nickel monosilicide could maintain a low resistance in wide temperature range and is considered suitable for the nano-thick silicide process.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.20 no.6
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• pp.254-261
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• 2010

Polycrystalline silicon (pc-Si) films are fabricated and characterized for application to pc-Si thin film solar cells as a seed layer. The amorphous silicon films are crystallized by the aluminum-induced layer exchange (ALILE) process with a structure of glass/Al/$Al_2O_3$/a-Si using various thicknesses of $Al_2O_3$ layers. In order to investigate the effects of the oxide layer on the crystallization of the amorphous silicon films, such as the crystalline film detects and the crystal grain size, the $Al_2O_3$ layer thickness arc varied from native oxide to 50 nm. As the results, the defects of the poly crystalline films are increased with the increase of $Al_2O_3$ layer thickness, whereas the grain size and crystallinity are decreased. In this experiments, obtained the average pc-Si sub-grain size was about $10\;{\mu}m$ at relatively thin $Al_2O_3$ layer thickness (${\leq}$ 16 nm). The preferential orientation of pc-Si sub-grain was <111>.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.22 no.5
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• pp.831-836
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• 2013

This study demonstrates the process of fabricating patterns using tribonanolithography (TNL),with laboratory-made micro polycrystalline diamond (PCD) tools that are attached to an atomic force microscope (AFM). The various patterns are easily fabricated using mechanical scratching, under various normal loads, using the PCD tool on single crystal silicon, which is the master mold for replication in this study. Then, polydimethylsiloxane (PDMS) replica molds are fabricated using precise pattern transfer processes. The transferred patterns show high dimensional accuracy as compared with those of TNL-processed silicon micro molds. TNL can reduce the need for high cost and complicated apparatuses required for conventional lithography methods. TNL shows great potential in that it allows for the rapid fabrication of duplicated patterns through simple mechanical micromachining on brittle sample surfaces.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.5 no.3
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• pp.299-305
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• 1995

Visible photoluminescing (PL) silicon at room temperature has been prepared by a dry technique, that is, by spark processing, contrary to anodically etched porous silicon. PL peak maximum of photoluminescing spark processed Si was shifted to blue 520 nm. The stability of spark processed Si towards degradation upon UV radiation was found to be extremely high. Results from high resolution TEM, XRD and XPS studies suggest that spark processed silicon involves minute nanocrystalline (polycrystalline) particles which are imbedded in an amorphous matrix, preferably $SiO_2$.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.413-418
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• 2006

Highly stable thin-film transistor (TFT) pixel employing both low temperature polycrystalline silicon (LTPS) and amorphous silicon (a-Si) for active matrix organic light emitting diode (AMOLED) is discussed. ELA (excimer laser annealing) LTPS-TFT pixel should compensate $I_{OLED}$ variation caused by the non-uniformity of LTPS-TFT due to the fluctuation of excimer laser energy and amorphous silicon TFT pixel is desired to suppress the decrease of $I_{OLED}$ induced by the degradation of a-Si TFT. We discuss various compensation schemes of both LTPS and a-Si TFT employing the voltage and the current programming.

• Electrical & Electronic Materials
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• v.10 no.8
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• pp.794-799
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• 1997

Poly-Si films have been prepared by solid phase crystallization of LPCVD(low-pressure CVD) amorphous silicon. The crystallinity of poly-Si films has been derived from UV reflectance spectrum and lies in the range between 70% and 80% . From XRD measurement the peak at 28.2$^{\circ}$from (111) plane is dominantly detected in the SPC poly-Si films, The average grain size of poly-Si film is determined by the image of SEM and varies from 4000 $\AA$ to 8000$\AA$. The electrical conductivity of as-deposited amorphous silicon film is about 2.5$\times$10$^{-7}$ ($\Omega$.cm)$^{-1}$ , and 3~4$\times$10$^{-6}$ ($\Omega$.cm)$^{-1}$ of room temperature conductivity is the SPC poly-Si films. The conductivity activation energies are 0.5~0.6 eV or the 500$\AA$-thick poly-Si films.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.2
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• pp.112-115
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• 2011

To stabilize the electric characteristic of Silicon Thin Film Transistor, reducing the current leakage is most important issue. To reduce the current leakage, many ideas were suggested. But the increase of mask layer also increased the cost. On this research Bird's Beak process was use to present element. Using Silvaco simulator, it was proven that it was able to reduce current leakage without mask layer. As a result, it was possible to suggest the structure that can reduce the current leakage to 1.39nA without having mask layer increase. Also, I was able to lead the result that electric characteristic (on/off current ratio) was improved compare from conventional structure.