• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.49 no.1
• /
• pp.24-29
• /
• 2000

We propose a simple method to control the crystallization depth of amorphous silicon (a-Si) deposited by PECVD or LPCVD during the excimer laser annealing (ELA). Employing the new method, we have formed poly-Si/a-Si double film and fabricated a new poly-Si TFT with vertical a-Si offsets between the poly-Si channel and the source/drain of TFT without any additional photo-lithography process. The maximum leakage current of the new poly-Si TFT decreased about 80% due to the highly resistive vertical a-Si offsets which reduce the peak electric field in drain depletion region and suppress electron-hole pair generation. In ON state, current flows spreading down through broad a-Si cross-section in the vertical a-Si offsets and the current density in the drain depletion region where large electric field is applied is reduced. The stability of poly-Si TFT has been improved noticeably by suppressing trap state generation in drain region which is caused by high current density and large electric field. For example, ON current of the new TFT decreased only 7% at a stress condition where ON current of conventional TFT decreased 89%.

• Journal of the Korean Vacuum Society
• /
• v.9 no.4
• /
• pp.346-352
• /
• 2000

We investigated the oxidation behavior of poly $Si_{1-x}Ge_x$ films (X=0.15, 0.42) at $700^{\circ}C$ in wet oxidation ambients and analyzed the oxide by XPS, RBS, and cross-sectional TEM. In the case of poly $Si_{0.85}Ge_{0.15}$ films, $SiO_2$ was formed on the poly $Si_{1-x}Ge_x$ films and Ge was rejected from growing oxide, subsequently leading to the increase of Ge content. In the case of poly $Si_{0.58}Ge_{0.42}$ films, we found that $SiO_2-GeO_2$ were formed on the poly $Si_{1-x}Ge_x$ films due to high Ge content. Finally, we proposed the oxidation model of poly $Si_{1-x}Ge_x$ films.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.376-376
• /
• 2012

본 연구는 Poly-Si에 이온 주입된 Boron의 Activation 거동을 연구하고자 SLS (Sequential Lateral Solidification) Poly-Si과 ELA (Excimer Laser Annealing) Poly-Si의 활성화 거동을 비교 분석하였다. SLS 및 ELA 결정화 방법으로 제조된 Poly-Si을 모재로 비 질량 분리 방식의 ISD (Ion Shower Doping) System을 사용하여 2.5~7.0 kV까지 이온주입 하였다. 이온주입 후 두 가지의 열처리 방법, 즉, FA 열처리(Furnace Annealing)와 RTA 열처리(Rapid Thermal Annealing)를 사용하여 도펀트 활성화 열처리를 수행하고 이온주입 조건 및 활성화 열처리 방법에 따른 결함 회복 및 도펀트 활성화 거동의 변화를 관찰하였다. TRIM-code Simulation 결과 가속 이온 에너지와 조사량이 증가 할수록 이온주입 시 발생하는 결함의 양이 증가하는 것을 정량적으로 계산하였다. 실험 결과 결함의 양이 증가 할수록 Activation이 잘되는 것을 관찰할 수 있었다. SLS Poly-Si에 비하여 ELA Poly-Si의 경우 도펀트 활성화 열처리 후 활성화 효율이 높게 나타났다. 본 결과는 Grain Boundary의 역할과 밀접한 관계가 있으며 간단한 정성적인 Model을 제시하였다. 활성화 효율의 경우 RTA 열처리 시편이 FA 시편에 비하여 높은 것이 관찰되었다. 본 결과는 열처리 온도 및 시간에 따라 변화하는 Boron의 특이한 활성화 거동인 Reverse Annealing 효과에 기인하는 것으로 규명되었다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2007.06a
• /
• pp.93-94
• /
• 2007

다양한 LDD(lightly doped drain)에 따른 n-channel poly-Si TFT (thin film transistor)에 대하여 보고한다. 유리 기판 위에 ELA를 이용하여 만들어진 Polycrystalline silicon (poly-Si)은 TFT-LCD의 응용을 위한 재료로써 우수한 특성을 갖는다. 제작된 n-channel TFT는 절연층으로 $SiN_x$, $SiO_2$의 이중 구조를 갖는다. 다양한 LDD에 따른 n-channel poly-Si TFT의 문턱전압($V_{TH}$), ON/OFF 전류비 ($I_{ON}/I_{OFF}$), 포화전류($I_{DSAT}$)는 TFT의 보다 좋은 성능을 위해 연구된다. 짧은 LLD 길이를 가진 n-channel poly-Si TFT의 문턱전압은 작고, 포화전류의 값은 크다. 또한 긴 LLD 길이를 가진 n-channel poly-Si TFT는 작은 kink effect를 가진다.

• Journal of the Korean Ceramic Society
• /
• v.41 no.9
• /
• pp.637-641
• /
• 2004

We investigated the effects of SiH$_4$ gas on the surface of Hf-silicate films during the deposition of polycrystalline (poly) Si films and the thermal stability of sputtered Hf-silicate films in poly Si/Hf-silicate structure by using High Resolution Transmission Electron Microscopy (HR-TEM) and X-ray Photoelectron Spectroscopy (XPS). Hf-silicate films were deposited by using DC-mag-netron sputtering with Hf target and Si target and poly Si films were deposited at 600$^{\circ}C$ by using Low Pressure Chemical Vapor Deposition (LPCVD) with SiH$_4$ gas. After poly Si film deposition at 600$^{\circ}C$, Hf silicide layer was observed between poly Si and Hf-silicate films due to the reaction between active SiH$_4$ gas and Hf-silicate films. After annealing at 900$^{\circ}C$, Hf silicide, formed during the deposition of poly Si, changed to Hf-silicate and the phase separation of the silicate was not observed. In addition, the Hf-silicate films remain amorphous phase.

• Journal of Sensor Science and Technology
• /
• v.18 no.3
• /
• pp.207-209
• /
• 2009

This paper describes the characteristics of poly 3C-SiC micro resonators with $3{\times}10^{17}{\sim}1{\times}10^{19}cm^{-3}$ doping concentrations. The 1.2 ${\mu}m$ thick cantilever and the 0.4 ${\mu}m$ thick doubly clamped beam resonators with different lengths were fabricated using poly 3C-SiC thin films. The characteristics of poly 3C-SiC micro resonators were evaluated by quartz and a laser vibrometer in vacuum at room temperature. The resonant frequencies of micro resonators decreased with doping concentrations owing to reduction in the Young's modulus of poly 3C-SiC thin films. It was confirmed that the resonant frequencies of poly 3C-SiC resonators are controllable by doping concentrations. Therefore, poly 3C-SiC resonators could be applied to MEMS devices and bio/chemical sensor applications.

• Journal of Sensor Science and Technology
• /
• v.16 no.4
• /
• pp.319-323
• /
• 2007

This paper describes the mechanical characteristics of poly 3C-SiC thin films grown on Si wafers with thermal oxide. In this work, the poly 3C-SiC thin film was deposited by APCVD method using only Ar carrier gas and single precursor HMDS at $1100^{\circ}C$. The elastic modulus and hardness of poly 3C-SiC thin films were measured using nanoindentation. Also, the roughness of surface was investigated by AFM. The resulting values of elastic modulus E, hardness H and the roughness of the poly 3C-SiC film are 305 GPa, 26 GPa and 49.35 nm respectively. The mechanical properties of the grown poly 3C-SiC film are better than bulk Si wafers. Therefore, the poly 3C-SiC thin film is suitable for abrasion, high frequency and MEMS applications.

• Journal of the Korean Vacuum Society
• /
• v.12 no.2
• /
• pp.130-135
• /
• 2003

Polycrystalline silicon thin films have been used for low cost thin film device application. However, it was very difficult to fabricate high performance poly-Si at a temperature lower than $600^{\circ}C$ for glass substrate because the crystallization process technologies like conventional solid phase crystallization (SPC) require the number of high temperature (600-$1000^{\circ}C$) process. The objective of this paper is to grow poly-Si on flexible substrate using a rapid thermal crystallization (RTC) of amorphous silicon (a-Si) layer and make the high temperature process possible on molybdenum substrate. For the high temperature poly-Si growth, we deposited the a-Si film on the molybdenum sheet having a thickness of 150 $\mu\textrm{m}$ as flexible and low cost substrate. For crystallization, the heat treatment was performed in a RTA system. The experimental results show the grain size larger than 0.5 $\mu\textrm{m}$ and conductivity of $10^{-5}$ S/cm. The a-Si was crystallized at $1050^{\circ}C$ within 3min and improved crystal volume fraction of 92 % by RTA. We have successfully achieved a field effect mobility over 67 $\textrm{cm}^2$/Vs.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 1997.10a
• /
• pp.88-88
• /
• 1997

• Electrical & Electronic Materials
• /
• v.9 no.1
• /
• pp.30-37
• /
• 1996

Previously, crystallization of a-Si:H films on glass substrates were limited to anneal temperature below 600.deg. C, over 10 hours to avoid glass shrinkage. Our study indicates that the crystallization is strongly influenced by anneal temperature and weakly affected by anneal duration time. Because of the high temperature process and nonconducting substrate requirements for poly-Si TFTs, the employed substrates were limited to quartz, sapphire, and oxidized Si wafer. We report on poly-Si TFT's using high temperature anneal on a Si:H/Mo structures. The metal Mo substrate was stable enough to allow 1000.deg. C anneal. A novel TFT fabrication was achieved by using part of the Mo substrate as drain and source ohmic contact electrode. The as-grown a-Si:H TFT was compared to anneal treated poly-Si TFT'S. Defect induced trap states of TFT's were examined using the thermally stimulated current (TSC) method. In some case, the poly-Si grain boundaries were passivated by hydrogen. A-SI:H and poly-Si TFT characteristics were investigated using an inverted staggered type TFT. The poly -Si films were achieved by various anneal techniques; isothermal, RTA, and excimer laser anneal. The TFT on as grown a-Si:H exhibited a low field effect mobility, transconductance, and high gate threshold voltage. Some films were annealed at temperatures from 200 to >$1000^{\circ}C$ The TFT on poly-Si showed an improved $I_on$$I_off$ ratio of $10_6$, reduced gate threshold voltage, and increased field effect mobility by three orders. Inverter operation was examined to verify logic circuit application using the poly Si TFTs.