• 대한기계학회논문집B
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• 제36권10호
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• pp.1019-1023
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• 2012

본 연구에서는 새로운 알루미늄 유도 결정화 공정을 제안하였다. 알루미늄 박막에 직접 3 A의 정전류를 인가하여 $1cm{\times}1cm$ 넓이의 두께 200 nm 비정질 실리콘 박막을 수십 초 내에 결정화하는 방법이다. 결정화된 다결정 실리콘 박막은 520 $cm^{-1}$ 에서의 라만 분광 피크를 통해 확인할 수 있었다. 공정 후, 알루미늄이 식각된 다결정 실리콘 박막은 다공성 구조임을 SEM 을 통하여 확인할 수 있었다. 또 한, 이차이온질량분석(secondary ion mass spectroscopy)에서 알루미늄 농도가 $10^{21}cm^{-3}$으로 헤비 도핑된 것을 확인 할 수 있었으며, 실시간으로 측정된 열화상 카메라의 결과를 통해 결정화는 820 K 근처에서 일어나는 것을 확인할 수 있었다.

• 한국전기전자재료학회논문지
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• 제36권3호
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• pp.233-240
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• 2023

p-type Tunnel Oxide Passivating Contacts (TOPCon) solar cell is fabricated with a poly-Si/SiO_x structure. It simultaneously achieves surface passivation and enhances the carriers' selective collection, which is a promising technology for conventional solar cells. The quality of passivation is depended on the quality of the tunnel oxide layer at the interface with the c-Si wafer, which is affected by the bond of SiO formed during the subsequent annealing process. The highest cell efficiency reported to date for the laboratory scale has increased to 26.1%, fabricated by the Institute for Solar Energy Research. The cells used a p-type float zone silicon with an interdigitated back contact (IBC) structure that fabricates poly-Si and SiO_x layer achieves the highest implied open-circuit voltage (iV_oc) is 750 mV, and the highest level of edge passivation is 40%. This review presents an overview of p-type TOPCon technologies, including the ultra-thin silicon oxide layer (SiO_x) and poly-silicon layer (poly-Si), as well as the advancement of the SiO_x and poly-Si layers. Subsequently, the limitations of improving efficiency are discussed in detail. Consequently, it is expected to provide a basis for the simplification of industrial mass production.

• 한국재료학회지
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• 제22권4호
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• pp.190-194
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• 2012

The formation of high-quality polycrystalline silicon (poly-Si) on relatively low cost substrate has been an important issue in the development of thin film solar cells. Poly-Si seed layers were fabricated by an inverse aluminum-induced crystallization (I-AIC) process and the properties of the resulting layer were characterized. The I-AIC process has an advantage of being able to continue the epitaxial growth without an Al layer removing process. An amorphous Si precursor layer was deposited on Corning glass substrates by RF magnetron sputtering system with Ar plasma. Then, Al thin film was deposited by thermal evaporation. An $SiO_2$ diffusion barrier layer was formed between Si and Al layers to control the surface orientation of seed layer. The crystallinity of the poly-Si seed layer was analyzed by Raman spectroscopy and x-ray diffraction (XRD). The grain size and orientation of the poly-Si seed layer were determined by electron back scattering diffraction (EBSD) method. The prepared poly-Si seed layer showed high volume fraction of crystalline Si and <100> orientation. The diffusion barrier layer and processing temperature significantly affected the grain size and orientation of the poly Si seed layer. The shorter oxidation time and lower processing temperature led to a better orientation of the poly-Si seed layer. This study presents the formation mechanism of a poly seed layer by inverse aluminum-induced crystallization.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.287-298
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• 2007

A two-dimensional treatment of the potential distribution under the depletion approximation is presented for poly-crystalline silicon thin film transistors. Green's function approach is adopted to solve the two-dimensional Poisson's equation. The solution for the potential distribution is derived using Neumann's boundary condition at the silicon-silicon di-oxide interface. The developed model gives insight into device behavior due to the effects of traps and grain-boundaries. Also short-channel effects and drain induced barrier lowering effects are incorporated in the model. The potential distribution and electric field variation with various device parameters is shown. An analysis of threshold voltage is also presented. The results obtained show good agreement with simulated results and numerical modeling based on the finite difference method, thus demonstrating the validity of our model.

• 센서학회지
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• 제18권2호
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• pp.147-153
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• 2009

A thermal flow sensor has been fabricated and characterized, consisting of a center resistive heater surrounded by two upstream and one downstream temperature sensing resistors. The heater and temperature sensing resistors are fabricated from nitrogen-doped(n-type) polycrystalline silicon carbide(poly-SiC) deposited by LPCVD(low pressure chemical vapor deposition) on LPCVD silicon nitride films on a Si substrate. Cavities were etched into the Si substrate from the front side to create suspended silicon nitride membranes carrying the poly-SiC elements. One upstream sensor is located $50{\mu}m$ from the heater and has a sensitivity of $0.73{\Omega}$/sccm with ${\sim}15\;ms$ rise time in a dynamic range of 1000 sccm. N-type poly-SiC has a linear negative temperature coefficient and a TCR(temperature coefficient of resistance) of $-1.24{\times}10^{-3}/^{\circ}C$ from room temperature to $100^{\circ}C$.

• 한국표면공학회지
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• 제43권1호
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• pp.7-11
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• 2010

Solid phase crystallization (SPC) is a simple method in producing a polycrystalline phase by annealing amorphous silicon (a-Si) in a furnace environment. Main motivation of the crystallization technique is to fabricate low temperature polycrystalline silicon thin film transistors (LTPS-TFTs) on a thermally susceptible glass substrate. Studies on SPC have been naturally focused to the low temperature regime. Recently, fabrication of polycrystalline silicon (poly-Si) TFT circuits from a high temperature polycrystalline silicon process on steel foil substrates was reported. Solid phase crystallization of a-Si films proceeds by nucleation and growth. After nucleation polycrystalline phase is propagated via twin mediated growth mechanism. Elliptically shaped grains, therefore, contain intra-granular defects such as micro-twins. Both the intra-granular and the inter-granular defects reflect the crystallinity of SPC poly-Si. Crystallinity and SPC kinetics of high temperatures were compared to those of low temperatures using Raman analysis newly proposed in this study.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제53권5호
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• pp.237-241
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• 2004

Amorphous silicon (a-Si) films are used in a broad range of solar cell, flat panel display, and sensor. Because of the greater ease of deposition and lower processing temperature, thin films are widely used for thin film transistors (TFTs). However, they have lower stability under the exposure of visible light and because of their low field effect mobility ($\mu$$_{FE}$ ) , less than 1 c $m^2$/Vs, they require a driving IC in the external circuits. On the other hand, polycrystalline silicon (poly-Si) thin films have superiority in $\mu$$_{FE}$ and optical stability in comparison to a-Si film. Many researches have been done to obtain high performance poly-Si because conventional methods such as excimer laser annealing, solid phase crystallization and metal induced crystallization have several difficulties to crystallize. In this paper, a new crystallization process using a molybdenum substrate has been proposed. As we use a flexible substrate, high temperature treatment and roll-to-roll process are possible. We have used a high temperature process above 75$0^{\circ}C$ to obtain poly-Si films on molybdenum substrates by a rapid thermal annealing (RTA) of the amorphous silicon (a-Si) layers. The properties of high temperature crystallized poly-Si studied, and poly-Si has been used for the fabrication of TFT. By this method, we are able to achieve high crystal volume fraction as well as high field effect mobility.

• Bulletin of the Korean Chemical Society
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• 제32권7호
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• pp.2227-2232
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• 2011

The new metrology, Advanced Poly-silicon Ultra-Trace Profiling (APUTP), was developed for measuring bulk Cu and Ni in heavily boron-doped silicon wafers. A Ni recovery yield of 98.8% and a Cu recovery yield of 96.0% were achieved by optimizing the vapor phase etching and the wafer surface scanning conditions, following capture of Cu and Ni by the poly-silicon layer. A lower limit of detection (LOD) than previous techniques could be achieved using the mixture vapor etching method. This method can be used to indicate the amount of Cu and Ni resulting from bulk contamination in heavily boron-doped silicon wafers during wafer manufacturing. It was found that a higher degree of bulk Ni contamination arose during alkaline etching of heavily boron-doped silicon wafers compared with lightly boron-doped silicon wafers. In addition, it was proven that bulk Cu contamination was easily introduced in the heavily boron-doped silicon wafer by polishing the wafer with a slurry containing Cu in the presence of amine additives.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.1549_1550
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• 2009

본 연구에서는 적외선 가스 센서용 IR source에 대한 연구를 진행하였다. MEMS 공정을 이용하여 poly-silicon을 IR source의 발열체로 사용하였다. Chip size는 $2{\times}2mm$ 이며 membrane의 면적은 $1{\times}1mm$로 설계, 제작 하였다. 제작된 IR source의 적외선 방출 특성을 적외선 카메라를 이용하여 관찰하였으며, 같은 온도에서의 thermal stress에 대한 관찰도 진행하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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• pp.303-306
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• 2005

We report the self-aligned low temperature poly silicon (LTPS) TFT process using simple doping process. In conventional LTPS-TFT, the Lightly Doped Drain (LDD) doping and source/drain doping are processed separately by aligning the gate with the source and drain during the gate lithography step. This ne w process not only fabricates fully self-aligned low temperature poly silicon TFTs with symmetric LDD structure but also simplifies the process flow with combined source/drain doping and LDD doping in one step. LDD doping process can be achieved using only source/drain doping process according to the new structure. In this paper, the TFT characteristics of NMOS and PMOS using the new doping process will be discussed.