• Electrical & Electronic Materials
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• v.11 no.11
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• pp.22-27
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• 1998

We have investigated the effect of an ion shower doping of the laser annealed poly-Si films at an elevated substrate temperatures. The substrate temperature was varied from room temperature to 300$^{\circ}C$ when the poly-Si film was doped with phosphorus by a non-mass-separated ion shower. Optical, structural, and electrical characterizations have been performed in order to study the effect of the ion showering doping. The sheet resistance of the doped poly-Si films was decreased from7${\times}$106 $\Omega$/$\square$ to 700 $\Omega$/$\square$ when the substrate temperature was increased from room temperature to 300$^{\circ}C$. This low sheet resistance is due to the fact that the doped film doesn't become amorphous but remains in the polycrystalline phase. The mildly elevated substrate temperature appears to reduce ion damages incurred in poly-Si films during ion-shower doping. Using the ion-shower doping at 250$^{\circ}C$, the field effect mobility of 120 $\textrm{cm}^2$/(v$.$s) has been obtained for the n-channel poly-Si TFTs.

• 한국정보디스플레이학회:학술대회논문집
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• 2000.01a
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• pp.67-68
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• 2000

Polycrystalline silicon (poly-Si) thin film transistors (TFT's) employing vertical amorphous silicon (a-Si) offsets have been fabricated without additional photolithography processes. The a-Si offset has been formed utilizing the poly-Si grain growth blocking effect by thin native oxide film during the excimer laser recrystallization of a-Si. The ON current degradation of the new device after 4 hour's electrical stress was reduced by 5 times compared with conventional poly-Si TFT's.

• Journal of Sensor Science and Technology
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• v.26 no.6
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• pp.438-444
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• 2017

In this paper, we focus on optimization of the in-situ phosphorous (P) doping of low-pressure chemical vapor deposited (LPCVD) poly Si resistors for obtaining near-zero temperature coefficient of resistance (TCR) at temperature range from 25 to $600^{\circ}C$. The deposited poly Si films were annealed by rapid thermal anneal (RTA) process at the temperature range from 900 to $1000^{\circ}C$ for 90s in nitrogen ambient to relieve intrinsic stress and decrease the TCR in the poly Si layer and get the Ohmic contact. After the RTA process, a roughness of the thin film was slightly changed but the grain size and crystallinity of the thin film with the increase in anneal temperature. The film annealed at $1,000^{\circ}C$ showed the behavior of Schottky contact and had dislocations in the films. Ohmic contact and TCR of $334.4{\pm}8.2$ (ppm/K) within 4 inch wafer were obtained in the measuring temperature range of 25 to $600^{\circ}C$ for the optimized 200 nm thick-poly Si film with width/length of $20{\mu}m/1,800{\mu}m$. This shows the potential of in-situ P doped LPCVD poly Si as a resistor for pressure sensor in harsh environment applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.354-357
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• 2002

Thermally grown gate oxide on 4H-SiC wafer was investigated. The oxide layers were grown at l150$^{\circ}C$ varying the carrier gas and post activation annealing conditions. Capacitance-Voltage(C-V) characteristic curves were obtained and compared using various gate electrode such as Al, Ni and poly-Si. The interface trap density can be reduced by using post oxidation annealing process in Ar atmosphere. All of the samples which were not performed a post oxidation annealing process show negative oxide effective charge. The negative oxide effective charges may come from oxygen radical. After the post oxidation annealing, the oxygen radicals fixed and the effective oxide charge become positive. The effective oxide charge is negative even in the annealed sample when we use poly silicon gate. Poly silicon layer was dope by POCl$_3$ process. The oxide layer may be affected by P ions in poly silicon layer due to the high temperature of the POCl$_3$ doping process.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.4
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• pp.33-39
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• 1997

The crystallization temperature of an amorphous silicon (a-Si) can be lowered down to 400.deg. C by a new method : Double-metal induced lateral crystallization (DMILC). The a-Si film was laterally crystallized from Ni and Pd deposited area, and its lateral crystallization rate reaches up to 0.2.mu.m/hour at that temperature and depends on the overlap length of Ni and Pd films; the shorter the overlap length, the faster the rate. Poly-Silicon thin film transistors (poly-Si TFT's) fabricated by DMILC at 400.deg. C show a field effect mobility of 38.5cm$^{3}$/Vs, a minimum leakage current of 1pA/.mu.m, and a slope of 1.4V/dec. The overlap length does not affect the characteristics of the poly-Si TFT's, but determines the lateral crystallization rate.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.194-194
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• 2009

3C-SiC thin films are widely used in extreme environments, radio frequency (RF) environments, and bio-materials for micro/nano electronic mechanical systems (M/NEMS). The mechanical properties of 3C-SiC thin films need to be considered when designing M/NEMS, so Young's Modulus and the hardness need to be accurately measured. Young's Modulus and the hardness are influenced by N-doping. In this paper, we show that the mechanical properties of poly (polycrystalline) 3C-SiC thin films are influenced by the N-doping concentration. Furthermore, we measure the mechanical properties of 3C-SiC thin films for N-doping concentrations of 1%, 3%, and 5%, by using nanoindentation. For films deposited using a 1% N-doping concentration, Young's Modulus and the hardness were measured as 270 GPa and 30 GPa, respectively. When the surface roughness of the thin films was investigated by using atomic force microscopy (AFM), the roughness of the 5% N-doped 3C-SiC thin film was the lowest of all the films, at 15 nm.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04a
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• pp.169-172
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• 2000

A-Si:H and poly-Si TFT characteristics were investigated using an inverted staggered type TFT. The poly-Si films were achieved by various anneal techniques ; isothermal, RTA, and excimer laser anneal. The TFT on as-grown a-Si:H exhibited a low field effect mobility, transconductance, and high gate threshold voltage. Some films were annealed at temperatures from $200^{\circ}C$ to $1000^{\circ}C$. The TFT on poly-Si showed an improved $I_{on}/I_{off}$ ratio of $10^6$, reduced gate threshold voltage, and increased field effect mobility by three orders. Inverter operation was examined to verify logic circuit application using the poly-Si TFTs.

• 한국신재생에너지학회:학술대회논문집
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• 2010.06a
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• pp.96.2-96.2
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• 2010

The surface morphology and structural properties of polycrystalline silicon (poly-Si) films made in-situ aluminum induced crystallization at various substrate temperature (300~600) was investigated. Silicon films were deposited by hot-wire chemical vapor deposition (HWCVD), as the catalytic or pyrolytic decomposition of precursor gases SiH4 occurs only on the surface of the heated wire. Aluminum films were deposited by DC magnetron sputtering at room temperature. continuous poly-Si films were achieved at low temperature. from cross-section TEM analyses, It was confirmed that poly-Si above $450^{\circ}C$ was successfully grown on and poly-Si films had (111) preferred orientation. As substrate temperature increases, Si(111)/Si(220) ratio was decreased. The electrical properties of poly-Si film were investigated by Hall effect measurement. Poly-Si film was p-type by Al and resistivity and hall effect mobility was affected by substrate temperature.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.7
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• pp.606-610
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• 2007

This paper describes the Raman scattering characteristics of polycrystalline (poly) 3C-SiC thin films, in which they were deposited on the oxidized Si substrate by APCVD method according to growth temperature. Since the phonon modes were not measured for $0.4{\mu}m$ thick 3C-SiC, $2.0{\mu}m$ thick 3C-SiC deposited on the oxidized Si at $1180^{\circ}C$, in which TO (transverse optical mode) and LO (longitudinal optical mode) phonon modes were appeared at 794.4 and $965.7cm^{-1}$, respectively. The broad FWHM (full width half maximum) can explain that the crystallinity of 3C-SiC deposited at $1180^{\circ}C$ becomes polycrystalline instead of disorder crystal. Additionally, the ratio of intensity $I_{LO}/I_{TO}{\approx}1.0$ of 3C-SiC indicates that the crystal disorder of $3C-SiC/SiO_2/Si$ is small. Compared poly $3C-SiC/SiO_2$ with $SiO_2/Si$ interfaces, $1122.6cm^{-1}$ phonon mode was measured which may belong to C-O bonding and two phonon modes, 1355.8 and $1596.8cm^{-1}$ related to D and G bands of C-C bonding in the Raman range of 200 to $2000cm^{-1}$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.89-90
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• 2007

This paper presents the mechanical properties of 3C-SiC thin film according to 0, 7, and 10% carrier gas $(H_2)$ concentrations using Nano Indentation. When carrier gas $(H_2)$ concentration was 10%, it has been proved that the mechanical properties, elastic modulus and hardness, of 3C-SiC are the best of them. In the case of 10% carrier gas concentration, Young's modulus and Hardness were obtained as 367 GPa and 36 GPa, respectively. When the surface roughness according to $H_2$ concentrations was investigated by AFM (atomic force microscope), when $H_2$ concentration was 10%, the roughness of 3C-SiC thin was 9.92 nm, which is also the best of them. Therefore, in order to apply poly 3C-SiC thin film to MEMS applications, $H_2$ concentration's rate should increase to obtain better mechanical properties and surface roughness.