• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.11a
• /
• pp.276-279
• /
• 2004

Plasma enhanced chemical vapor deposition (PECVD) of silicon nitride (SiN) is a proven technique for obtaining layers that meet the needs of surface passivation and anti-reflection coating. In addition, the deposition process appears to provoke bulk passivation as well due to diffusion of atomic hydrogen. This bulk passivation is an important advantage of PECVD deposition when compared to the conventional CVD techniques. A further advantage of PECVD is that the process takes place at a relatively low temperature of 300t, keeping the total thermal budget of the cell processing to a minimum. In this work SiN deposition was performed using a horizontal PECVD reactor system consisting of a long horizontal quartz tube that was radiantly heated. Special and long rectangular graphite plates served as both the electrodes to establish the plasma and holders of the wafers. The electrode configuration was designed to provide a uniform plasma environment for each wafer and to ensure the film uniformity. These horizontally oriented graphite electrodes were stacked parallel to one another, side by side, with alternating plates serving as power and ground electrodes for the RF power supply. The plasma was formed in the space between each pair of plates. Also this paper deals with the fabrication of multicrystalline silicon solar cells with PECVD SiN layers combined with high-throughput screen printing and RTP firing. Using this sequence we were able to obtain solar cells with an efficiency of 14% for polished multi crystalline Si wafers of size 125 m square.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2003.03a
• /
• pp.35-35
• /
• 2003

Recent progress in the integration of the ferroelectric random access memories (FRAM) has attracted much interest. Strontium bismuth tantalate(SBT) is one of the most attractive materials for use in nonvolatile-memory applications due to low-voltage operations, low leakage current, and its excellent fatigue-free property. High-density FRAMs operated at a low voltage below 1.5V are applicable to mobile devices operated by battery. SBT films thinner than 0.1 #m can be operated at a low voltage, because the coercive voltage (Vc) decreases as the film thickness is reduced. In addition, the thickness of the SBT film will have to be reduced so it can fit between adjacent storage nodes in a pedestal type capacitor in future FRAMs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2003.04a
• /
• pp.111-114
• /
• 2003

Compared to a conventional atomic layer deposition (ALD) grown Al203 film, Plasma enhanced ALD (PEALD) grown AION film was revealed to possess a large breakdown field, which is necessary for stable operation of thin film electroluminescent (TFEL) device. Also, AION is more stable than Al203 films grown by PEALD or by ALD after post-annealing process, which is inevitably required to improve luminance property of phosphor. Furthermore, AION films were applied to insulators of ZnS:Tb TFEL device. Resultant1y, they show better stability than ALD grown insulators under high electric field.

• Proceedings of the Korean Institute of Surface Engineering Conference
• /
• 2009.05a
• /
• pp.182-183
• /
• 2009

플라즈마 원자층 증착법을 이용하여 Ru-TiN 빅막을 합성하였다. 박막 내 Ru의 함량은 Ru의 unit-cycle의 수에 따라 선형적으로 증가하였으며, Ru 함량이 증가함에 따라 박막의 비저항을 $3700{\mu}{\Omega}{\cdot}cm$에서 $190{\mu}{\Omega}{\cdot}cm$까지 자유롭게 조절할 수 있었다. Ru의 함량이 0.40 이상인 경우, Ru과 TiN 두물질이 교차 증착되어 서로의 결정 성장을 충분히 억제함으로서, 비정질구조를 가짐을 확인할 수 있었다. 또한, $O_2$ 분위기에서 열처리를 진행한 결과, Ru의 조성비가 0.40이상인 경우 $700^{\circ}C$까지 면저항의 변화가 거의 없음을 확인할 수 있었다.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2005.07a
• /
• pp.269-271
• /
• 2005

Using optimized sputtering condition of a-Si and $SiO_2$ thin film, we can obtained the large grained poly-Si film on PES substrate. The gate dielectric grown by plasma enhanced atomic layer deposition, laser activation and organic interlayer dielectric material make TFTs on PES possible with mobility of $11cm^2/Vs$ (nMOS) and $7cm_2/Vs$ (pMOS).

• Proceedings of the Korean Vacuum Society Conference
• /
• 2013.02a
• /
• pp.538-539
• /
• 2013

여러 장점으로 인해 OLED는 디스플레이 및 조명 등 적용분야가 넓어지고 있지만, 수분 및 산소에 취약하여 그 수명이 제한되는 단점이 있다. 이를 해결하고자 현재까지는 glass cap을 이용한 encapsulation 기술이 적용되고 있지만, flexible 기판에 적용하지 못하는 문제가 있다. 이러한 문제를 해결하고자 여러 가지 thin film encapsulation 기술이 적용되고 있으나 보다 신뢰성이 높은 기술의 개발이 절실한 때이다. Encapsulation 무기 박막 물질로서 $Si_3N_4$ 박막은 PE-CVD (Plasma Enhanced Chemical Vapor Deposition) 등의 박막 증착법을 사용한 많은 연구가 진행되어, 저온에서의 좋은 품질의 박막 증착이 가능하지만, 100도 이하의 thermal budget을 갖는 OLED Encapsulation에 사용하기에는 충분하지 않았다. CVD 박막의 특성을 더욱 개선하기 위해 최근 ALD (Atomic Layer Deposition) 방법을 통한 $Al_2O_3$ film 증착 방법이 연구되고 있지만, 낮은 증착 속도로 인해 양산에 걸림돌이 되고 있다. 본 연구에서는 또 다른 해결책으로서 Digital CVD 방법을 이용한 양질의 $Si_3N_4$ 박막의 증착을 연구하였다. 이것은 ALD 증착법과 유사하며, 1st step에서 PECVD 방법으로 4~5 ${\AA}$의 얇은 silicon 박막을 증착하고, 2nd step에서 nitrogen plasma를 이용하여 질화 반응을 진행하고, 이러한 cycle을 원하는 두께가 될 때까지 반복적으로 진행된다. 이 때 1 cycle 당 증착속도는 7 ${\AA}$/cycle 정도였다. 최적의 증착 방법과 조건으로 기존의 CVD $Si_3N_4$ 박막 대비 1/5 이하로 pinhole을 최소화 할 수는 있지만 완벽하게 제거하기는 힘든 문제가 있고, 이를 해결하기 위한 개선을 위한 접근 방법이 필요하다고 판단하였다. 본 연구에서는 무기물 박막인 carbon nitride를 이용한 SiN/C:N multilayer 증착 연구를 진행하였다. Fig. 1은 CVD 조건으로 증착된 두께 750 nm SiN film에서 여러 층의 C:N film layer를 삽입했을 때, 38 시간의 85%/$85^{\circ}C$ 가속실험에 따라 OLED의 발광 사진이다. 그림에서 볼 수 있듯이 C:N 층을 삽입하고 또한 그 박막의 수가 증가함에 따라서 OLED에 대한 encapsulation 특성이 크게 개선됨을 확인할 수 있다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.26 no.3
• /
• pp.177-182
• /
• 2013

Transparent thin film transistors (TTFT) were fabricated on $N^+$ Si wafers. $SiO_2$, $Si_3N_4/SiO_2$ and $Al_2O_3/SiO_2$ grown on the wafers were used as gate insulators. The rf magnetron sputtered zinc tin oxide (ZTO) films were adopted as active layers. $N^+$ Si wafers were wet-oxidized to grow $SiO_2$. $Si_3N_4$ and $Al_2O_3$ films were deposited on the $SiO_2$ by plasma enhanced chemical vapor deposition (PECVD) and atomic layer deposition (ALD), respectively. The mobility, $I_{on}/I_{off}$ and subthreshold swing (SS) were obtained from the transfer characteristics of TTFTs. The properties of gate insulators were analyzed by comparing the characteristics of TTFTs. The property variation of the ZTO TTFTs with time were observed.

• Korean Journal of Materials Research
• /
• v.23 no.10
• /
• pp.550-554
• /
• 2013

As continued scaling becomes increasingly difficult, 3D integration has emerged as a viable solution to achieve higher bandwidths and good power efficiency. 3D integration can be defined as a technology involving the stacking of multiple processed wafers containing integrated circuits on top of each other with vertical interconnects between the wafers. This type of 3D structure can improve performance levels, enable the integration of devices with incompatible process flows, and reduce form factors. Through silicon vias (TSVs), which directly connect stacked structures die-to-die, are an enabling technology for future 3D integrated systems. TSVs filled with copper using an electro-plating method are investigated in this study. DC and pulses are used as a current source for the electro-plating process as a means of via filling. A TiN barrier and Ru seed layers are deposited by plasma-enhanced atomic layer deposition (PEALD) with thicknesses of 10 and 30 nm, respectively. All samples electroplated by the DC current showed defects, even with additives. However, the samples electroplated by the pulse current showed defect-free super-filled via structures. The optimized condition for defect-free bottom-up super-filling was established by adjusting the additive concentrations in the basic plating solution of copper sulfate. The optimized concentrations of JGB and SPS were found to be 10 and 20 ppm, respectively.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.5 no.2
• /
• pp.107-112
• /
• 2005

We present an AlGaN/GaN metal-insulator-semiconductor-heterostructure field effect transistor (MIS-HFET) with an $Al_2O_3-HfO_2$ laminated high-k dielectric, deposited by plasma enhanced atomic layer deposition (PEALD). Based on capacitance-voltage measurements, the dielectric constant of the deposited $Al_2O_3-HfO_2$ laminated layer was estimated to be as high as 15. The fabricated MIS-HFET with a gate length of 102 m exhibited a maximum drain current of 500 mA/mm and maximum tr-ansconductance of 125 mS/mm. The gate leakage current was at least 4 orders of magnitude lower than that of the reference HFET. The pulsed current-voltage curve revealed that the $Al_2O_3-HfO_2$ laminated dielectric effectively passivated the surface of the device.

• Korean Journal of Materials Research
• /
• v.15 no.10
• /
• pp.626-631
• /
• 2005

GaN-related compound semiconductors were grown on the corrugated interface substrate using a metalorganic chemical vapor deposition system to increase the optical power of white LEDs. The patterning of substrate for enhancing the extraction efficiency was processed using an inductively coupled plasma reactive ion etching system and the surface morphology of the etched sapphire wafer and that of the non-etched surface were investigated using an atomic force microscope. The structural and optical properties of GaN grown on the corrugated interface substrate were characterized by a high-resolution x-ray diffraction, transmission electron microscopy, atomic force microscope and photoluminescence. The roughness of the etched sapphire wafer was higher than that of the non-etched one. The surface of III-nitride films grown on the hemispherically patterned wafer showed the nano-sized pin-holes that were not grown partially. In this case, the leakage current of the LED chip at the reverse bias was abruptly increased. The reason is that the hemispherically patterned region doesn't have (0001) plane that is favor for GaN growth. The lateral growth of the GaN layer grown on (0001) plane located in between the patterns was enhanced by raising the growth temperature ana lowering the reactor pressure resulting in the smooth surface over the patterned region. The crystal quality of GaN on the patterned substrate was also similar with that of GaN on the conventional substrate and no defect was detected in the interface. The optical power of the LED on the patterned substrate was $14\%$ higher than that on the conventional substrate due to the increased extraction efficiency.