• Smart Media Journal
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• v.6 no.3
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• pp.9-14
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• 2017

This paper is a study on the hardware implementation of the encryption and decryption block of the lightweight block cipher algorithm LEA which can be used for tiny devices in IoT environment. It accepts all secret keys with 128 bit, 192 bit, and 256 bit sizes and aims at the integrated implementation of encryption and decryption functions. It describes design results of applying pipeline method for performance enhancement. When a decryption function is executed, round keys are used in reverse order of encryption function. An efficient hardware implementation method for minimizing performance degradation are suggested. Considering the number of rounds are 24, 28, or 32 times according to the size of secret keys, pipeline of LEA is implemented so that 4 round function operations are executed in each pipeline stage.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.10
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• pp.49-56
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• 2010

In this paper, a low-power frequency offset synchronization structure using CORDIC algorithm is proposed. Main blocks of frequency offset synchronization are estimation and compensation block. In the proposed frequency offset estimation block, implementation area is reduced by using sequential CORDIC, and throughput is accelerated by using 2 step CORDIC. In the proposed frequency offset compensation block, pipeline CORDIC is utilized for area reduction and high speed processing. Through MatLab simulation, function for proposed structure is verified. Proposed frequency offset synchronization structure is implemented by Verilog-HDL coding and implementation area is estimated by Synopsys logic synthesis tool.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.171-174
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• 2000

This paper proposes a pipelined adaptive filter based on affine projection algorithm with order 2. This filter gives a better convergence performance than that of LMS or NLMS pipeline algorithm and has same latency with the pipeline algorithm based on equivalent transformation. Compared to the critical path of the pipeline NLMS implementation, only 2 additions are increased in that of the proposed implementation.

• Journal of the Semiconductor & Display Technology
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• v.23 no.2
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• pp.76-81
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• 2024

UC Berkeley developed RISC-V, which is an open-source Instruction Set Architecture. This paper proposes a 32-bit 6-stage pipeline architecture based on the RV32I RSIC-V. The performance of the proposed 6-stage pipeline architecture is compared with the existing 32-bit 5-stage pipeline architecture also based on the RV32I processor ISA to determine the impact of the number of pipeline stages on performance. The RISC-V processor is designed in Verilog-HDL and implemented using Quartus Prime 20.1. To compare performance the Dhrystone benchmark is used. Subsequently, peripherals such as GPIO, TIMER, and UART are connected to verify operation through an FPGA. The maximum clock frequency for the 5-stage pipeline processor is 42.02 MHz, while for the 6-stage pipeline processor, it was 49.9MHz, representing an 18.75% increase.

• Journal of the Korean Association of Geographic Information Studies
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• v.3 no.3
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• pp.90-97
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• 2000

The study was aimed to extract the improvement measures for the problem on GIS application GIS for water supply and sewerage pipeline facility management in the Jechon city. For this, it performed of analysis of their working and modeling with other relational contents of the water and sewer facility management. As the results, the implementation of water and sewer facility management system by use of GIS has to applying development through relational analysis not only pipeline facility and leaking water protection, pipeline network analysis but also digital topography, drawing data, water user's information.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.2
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• pp.197-208
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• 1996

A neural network-based PSRI(position, scale, and rotation invariant) feature extraction and ATR (automatic target recognition) system are proposed and an efficient parallel implementatio of the proposed system using multicomputer is also presented. In the proposed system, the scale and rotationinvariant features are extracted from the contour projection of the number of edge pixels on each of the concentric circles, which is input t the cooperative network. We proposed how to decide the optimum depth and the width of the parallel pipeline system for real time applications by modeling the proposed system into a parallel pipeline implementation method using transputers is also proposed. The implementation results show that we can extract PSRI features less sensitive to input variations, and the speedup of the proposed ATR system is about 7.55 for the various rotated and scaled targets using 8-node transputer system.

• Journal of Mechanical Science and Technology
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• v.17 no.5
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• pp.629-636
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• 2003

This paper introduces the developed geometry PIG (Pipeline Inspection Gauge), one of several ILI (In-Line Inspection) tools, which provide a full picture of the pipeline from only single pass, and has compact size of the electronic device with not only low power consumption but also rapid response of sensors such as calipers, IMU and odometer. This tool is equipped with the several sensor systems. Caliper sensors measure the pipeline internal diameter, ovality and dent size and shape with high accuracy. The IMU (Inertial Measurement Unit) measures the precise trajectory of the PIG during its traverse of the pipeline. The IMU also provide three-dimensional coordination in space from measurement of inertial acceleration and angular rate. Three odometers mounted on the PIG body provide the distance moved along the line and instantaneous velocity during the PIG run. The datum measured by the sensor systems are stored in on-board solid state memory and magnetic tape devices. There is an electromagnetic transmitter at the back end of the tool, the transmitter enables the inspection operators to keep tracking the tool while it travels through the pipeline. An experiment was fulfilled in pull-rig facility and was adopted from Incheon LT (LNG Terminal) to Namdong GS (Governor Station) line, 13 km length.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.153-156
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• 2002

FFT/IFFT block is very important module to determine the performance of OFDM system. This block has been implemented using several FFT algorithms such as radix-2, radix-4 etc. However SRFFT algorithm has not been implemented because of the complexity for implementation. This paper proposes a serial-pipeline SRFfT for OFDM system. The serial-pipeline SRFFT is optimized to use a serial input and serial output. We have implemented the SRFFT block using anam 0.25 Um five-metal process. The simulation show that the SRFFT block can operate about 200MHz. This architecture could be adapted to IEEE 802.lla wireless LAN standard.

• The Journal of the Korea Contents Association
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• v.13 no.8
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• pp.44-51
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• 2013

Raster operations are widely used to display full-color graphics images (or pixmaps) and single-color images (or bitmaps). These features are strongly needed for image processing applications and font output. However, current mobile graphics platforms, including OpenGL ES hardware implementations, do not directly support these features. To fully support those raster operations on the mobile graphics platforms, we interpreted the graphics images as a set of 3D points, and processed those 3D points through the typical 3D geometry pipelines, in a full-software implementation. Our implementation shows sufficient execution speeds, and passed the official conformance tests to show its correctness.

• The Magazine of the IEIE
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• v.23 no.11
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• pp.89-100
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• 1996

A new stage-sliced pipiline structure is presented to design a high speed real time Global Positional Systems(GPS) applications. The CORDIC algorothm was revised to generate a pipeline structure, which will be used to produce a large amount of trigonometric computations rapidly. A stage-sliced approach was introduced to adjust the number of interative processes, and thereby to control the precision of computation results. Both the computation and the control circuits of the proposed architecture are included in a pipeline stage, which are intergrated into a stage slice. The circuit was prototyped using six FPGA chips : one is used for glue logics and five of the chips are used for pipeline slice implementation. A single FPGA chip comprising 7 pipeline stages provides one pipeline slice. To compensate and inter-slice time delay, dummy cycles are introduced in inter-slice signal exchanges.