• Journal of IKEEE
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• v.20 no.1
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• pp.75-81
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• 2016

This paper proposes a design of the tile based on graphic pipeline to improve the graphic application performance in SIMT based GP-GPU. The proposed Tile based on graphics pipeline avoids unnecessary graphic processing operation, and processes the rasterization step in parallel. The massive data processing in parallel through SIMT architecture improve the computational performance, thereby improving the 3D graphic pipeline performance. The more vertex data of 3D model, the higher performance. The proposed structure was confirmed to improve processing performance of up to 3 times from about 1.18 times as compared to 'RAMP' and previous studies.

• Journal of the Korea Society of Computer and Information
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• v.10 no.3 s.35
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• pp.183-188
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• 2005

Parallel processing in block cryptographic algorithm is difficult, because Feistel structure that is basis structure of block cryptographic algorithm is sequential processing structure. Therefore this paper changes these sequential processing structure and Feistel structure made parallel processing to be possible. This paper that apply this modified structure designed DES that have parallel Feistel structure. Proposed parallel Feistel structure could prove greatly block cryptographic algorithm's performance such as DES and so on that could not but have trade-off relation the data processing speed and data security interval because block cryptographic algorithm can not use pipeline method because of itself structural problem. Therefore, modified Feistel structure is going to display more superior security function and processing ability of high speed than now in case apply way that is proposed to SEED, AES's Rijndael, Twofish etc. that apply Feistel structure.

• Journal of Astronomy and Space Sciences
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• v.20 no.4
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• pp.403-416
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• 2003

There are common features, in both imaging surveys and image processing, between astronomical observations and remote sensing. Handling large amounts of data, in an easy and fast way, has become a common issue. Implementing pipeline software can be a solution to the problem, one which allows the processing of various kinds of data automatically. As a case study, the development of pipeline software for the EIS (European Southern Observatory Imaging Survey) is introduced. The EIS team has been conducting a sky survey to provide candidate targets to the 250 VLTs (Very Large Telescopes) observations. The survey data have been processed in a sequence of five major data corrections and reductions, i.e. preprocessing, flat fielding, photometric and astrometric corrections, source extraction, and coaddition. The processed data are eventually distributed to the users. In order to provide automatic processing of the vast volume of observed data, pipeline software has been developed. Because of the complexity of objects and different characteristic of each process, it was necessary to analyze the whole works of the EIS survey program. The overall tasks of the EIS are identified, and the scheme of the EIS pipeline software is defined. The system structure and the processes are presented, and in-depth flow charts are analyzed. During the analyses, it was revealed that handling the data flow and managing the database are important for the data processing. These analyses may also be applied to many other fields which require image processing.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.10
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• pp.49-56
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• 2010

In this paper, a low-power frequency offset synchronization structure using CORDIC algorithm is proposed. Main blocks of frequency offset synchronization are estimation and compensation block. In the proposed frequency offset estimation block, implementation area is reduced by using sequential CORDIC, and throughput is accelerated by using 2 step CORDIC. In the proposed frequency offset compensation block, pipeline CORDIC is utilized for area reduction and high speed processing. Through MatLab simulation, function for proposed structure is verified. Proposed frequency offset synchronization structure is implemented by Verilog-HDL coding and implementation area is estimated by Synopsys logic synthesis tool.

• Convergence Security Journal
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• v.16 no.7
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• pp.113-120
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• 2016

This paper presents a new high-speed SHA-1 pipeline architecture having a computation delay close to the maximum critical path delay of the original SHA-1. The typical SHA-1 pipelines are based on either a hash operation or unfolded hash operations. Their throughputs are greatly enhanced by the parallel processing in the pipeline, but the maximum critical path delay will be increased in comparison with the unfolding of all hash operations in each round. The pipeline stage logics in the proposed SHA-1 has the latency is similar with the result of dividing the maximum threshold delay of a round by the number of iterations. Experimental results show that the proposed SHA-1 pipeline structure is 0.99 and 1.62 at the operating speed ratio according to circuit size, which is superior to the conventional structure. The proposed pipeline architecture is expected to be applicable to various cryptographic and signal processing circuits with iterative operations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.12
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• pp.2675-2680
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• 2010

Computation steps for 3D graphic processing consist of two stages - fixed operation stage and programming required stage. Using this characteristic of 3D pipeline, a hybrid structure between graphics hardware designed by fixed structure and programmable hardware based on instructions, can handle graphic processing more efficiently. In this paper, fragment Shader is designed under this hybrid structure. It also supports OpenGL ES 2.0. Interior interface is optimized to reduce the delay of entire pipeline, which may be occurred by data I/O between the fixed hardware and the Shader. Interior register group of the Shader is designed by an interleaved structure to improve the register space and processing speed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.4
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• pp.287-292
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• 2010

Effect of conductance factors on performance of vacuum system was simulated for optimum design of vacuum system. In this investigation, the feasibility of modeling mechanism for VacSim$^{Multi}$ simulator was proposed. Application specific design of vacuum system is required to meet the particular process conditions for various industrial implementations of vacuum equipments. Geometry and length, diameter of exhaust pipeline were modeled as simulation modeling variables for conductance effects. Series vacuum system was modeled and simulated with varied dimensions and structures of exhaust pipeline. Variation of pipeline diameter showed the more significant effects on vacuum characteristics than that of pipeline length variations. It was also observed that the aperture structure of pipeline had the superior vacuum characteristics among the modeled systems.

• The Journal of Korea Robotics Society
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• v.5 no.3
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• pp.251-261
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• 2010

In this paper, we introduce an internal pipeline exploration of an in-pipe robot, based on the landmark recognition system. The fittings of pipelines such as elbows and branches are used as the landmarks. The robot recognizes the landmarks with a vision system by using the shadows of the elements, which are generated by the specially designed illuminator on the robot. By using a simple image-processing, the robot can easily detect and distinguish these landmarks while recognizing the direction of the pipeline path. Simultaneously, all information for exploration is continuously recorded and used to reconstruct the map of the pipelines. The effectiveness of the proposed method is verified by real experiments using the in-pipe robot MRINSPECT V for moving inside of the miniature urban 8-inch gas pipeline structure.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.283-290
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• 2006

The cellular neural networks have the structure that consists of an array of the same cell which is a simple processing element, and each of the cells has local connectivity and space invariant template properties. So, it has a very suitable structure for the hardware implementation. But, it is impossible to have a one-to-one mapping between the CNN hardware processors and the pixels of the practical large image. In this paper, a $5{\times}5$ CNN hardware processor with pipeline input and output that can be applied to the time-multiplexing processing scheme, which processes the large image with a small CNN cell block, is designed. the operation of the implemented $5{\times}5$ CNN hardware processor is verified from the edge detection and the shadow detection experimentations.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.10
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• pp.36-42
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• 1997

In the whole world, the research about the VLSI implementation of motion estimation algorithm is progressed to actively full (brute force) search algorithm research with the development of systolic array possible to parallel and pipeline processing. But, because of processing time's limit in a field to handle a huge data quantily such as a high definition television, many problems are happened to full search algorithm. In the paper, as a fast processing to using parallel scheme for the serial input image data, motion estimator of systolic array structure verifying that processing time is improved in contrast to the conventional full search algorithm.