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http://dx.doi.org/10.6109/jkiice.2010.14.12.2675

A Design of Programmable Fragment Shader with Reduction of Memory Transfer Time  

Park, Tae-Ryoung (서경대학교 컴퓨터공학과)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.14, no.12, 2010 , pp. 2675-2680 More about this Journal
Abstract
Computation steps for 3D graphic processing consist of two stages - fixed operation stage and programming required stage. Using this characteristic of 3D pipeline, a hybrid structure between graphics hardware designed by fixed structure and programmable hardware based on instructions, can handle graphic processing more efficiently. In this paper, fragment Shader is designed under this hybrid structure. It also supports OpenGL ES 2.0. Interior interface is optimized to reduce the delay of entire pipeline, which may be occurred by data I/O between the fixed hardware and the Shader. Interior register group of the Shader is designed by an interleaved structure to improve the register space and processing speed.
Keywords
3D Graphics; Fragment Shader; OpenGL;
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