• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.55-60
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• 2020

The hard mask photo-resist strip inspection system for the semiconductor wafer manufacturing process inspects the position of the circuit pattern formed on the wafer by measuring the distance from the edge of the wafer to the strip processing area. After that, it is an inspection system that enables you to check the process status in real time. Process defects can be significantly reduced by applying a tester that has not been applied to the existing wafer strip process, edge etching process, and wafer ashing process. In addition, it is a technology for localizing semiconductor process inspection equipment that can analyze the outer diameter of the wafer and the state of pattern formation, which can secure process stability and improve wafer edge yield.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.948-951
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• 2005

New technology that reduces photolithography process steps from 4 to 3 in fabrication of TFT LCD is introduced. The core technology for 3mask-TFTs is the lift-off process [1], by which the PAS and PXL layer are formed simultaneously. To evaluate the stability of this lift-off process, outgases from photo resist on a substrate during ITO deposition and the quality of ITO film were analyzed and the conventional photo resist stripper machine which operates lift-off process was examined to see its ability to reduce particle problems of the machine. Through the development of total process and design for TFTs using this 3mask technology, panels in TN and IPS modes which exhibit same performances of a display using a conventional process were achieved. In addition, this process was already verified in the mass production line and now some products are being produced by the 3mask technology.

• Journal of Magnetics
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• v.12 no.2
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• pp.81-83
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• 2007

Etching of NiFe films covered with an organic photo-resist or Ti was successfully performed by an inductively coupled plasma-reactive ion etching (ICP-RIE) system using $CHF_3/O_2/NH_3$ discharges exchanging $CHF_3$ for $CH_4$ gas gradually. Experimental results showed that the organic photo-resist mask can be applied to the NiFe etching. In the case of the Ti metal mask, it was found that the etching-selectivity Ti against NiFe was significantly varied from 7.3 to ${\sim}0$ by changing $CHF_3/CH_4/O_2/NH_3$ to $CH_4/O_2/NH_3$ discharges used in the ICP-RIE system. These results show that the present RIE of NiFe was dominated by a chemical reaction rather than a physical sputtering.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.66-66
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• 2006

Development of ArF Photo-lithography process has proceeded with the increase of numerical aperature (NA) and the decrease of resist thickness. It makes many problems such as cost and process complexity. A novel spin-on hard mask system is proposed to overcome many problems Spin-on hard mask composed of two layers of siloxane and carbon. The optical thickness of two layers is designed from reflectivity measurement at specified n, k respectively. The property of photo-resist shows different results according to Si contents. Si-contents was measured XPS(X-ray Photoelectron spectroscopy).

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.12.1-12.1
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• 2009

For the micro conductive line, memory device fabrication process use many expensive processes such as manufactur-ing of photo mask, coating of photo resist, exposure, development, and etching. However, direct printing technology has the merits about simple and cost effective processes because nano-metal particles contained inks are directly injective without mask. And also, this technology has the advantage about fabrication of fine pattern line on various substrates such as FPCB, PCB, glass, polymer and so on. In this work, we have fabricated the fine and thick metal pattern line on flexible PCB substrate for the next generation electronic circuit using Ag nano-particles contained ink. To improve the line tolerance on flexible PCB, metal lines are fabricated by sequential prinitng method. Sequential printing method has vari-ous merits about fine, thick and high resolution pattern lines without bulge.

• Journal of the Optical Society of Korea
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• v.17 no.1
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• pp.73-80
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• 2013

In the process of lithography using ultra violet light sources for semiconductor devices, most of defects are made by sub-micrometer pollutants generated at photochemical reactions. We proposed and developed a novel vibration-insensitive on-axis interferometer with a sub-micrometer lateral resolution by using the interference between two beams: one scattered from defects and the other reflected from a reference area without defects. The proposed system was successfully demonstrated to detect a small Al defect of 0.5 ${\mu}m$ diameter within the inspection time of less than 30 minutes over the area of the photo-mask which is 6 inch by 6 inch square.

• Journal of the Optical Society of Korea
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• v.6 no.4
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• pp.180-184
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• 2002

In this study, we investigated mask errors, photo errors with attenuated phase shift mask and off-axis illumination, and etch errors in dry etch conditions. We propose that total process proximity correction (TPPC), a concept merging every process step error correction, is essential in a lithography process when minimum critical dimension (CD) is smaller than the wavelength of radiation. A correction rule table was experimentally obtained applying TPPC concept. Process capability of controlling gate CD in DRAM fabrication should be improved by this method.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.05a
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• pp.223-223
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• 2004

반도체 및 TFT LCD 제조 공정에서 핵심 공정인 Photo 공정은 PR(Photo Resist, 감광액) Coating -) Exposure(노광) -. Develop(현상)으로 이루어져 있다. 이중 Exposure 공정에 사용되는 장치가 노광장비이다. 노광장비는 Mask Aligner 라고도 불리는데, 그만큼 정렬기술이 노광장비에서는 중요하다. 반도체 및 TFT LCD 는 여러 충의 회로를 쌓아감으로써 층과 층간의 전기적 작용으로 생성되는 Tr.(Transistor) 또는 Diode 등의 수동소자를 집적하는 기술로 제조되는 것으로, 층과 층간의 전기적 작용이 설계한 바와 같이 이루어지기 위해선, 층과 층 사이의 정렬이 정확히 이루어져야 한다.(중략)

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.369-372
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• 2004

Photo-induced surface alignment is charming as a non-contact photo-patternable alignment technology which can be used in the next generation of displays, such as large area, multi-domain. For decades, many polymer film have been investigated and developed to be used in the photo alignment. Among these photoreactive materials, recently developed polyimide, Chloromethylated Polyimide(CMPI) now became the focus of interests in this area because of its high photosensitivity and superior thermal stability. In this report, we present micro patterning method to form the nanoscale structure by Mask-Less laser patterning using this CMPI film and NSOM probe.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1085-1087
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• 1995

A large leakage current may be one of the critical issues for poly-silicon thin film transistors(poly-Si TFTs) for LCD applications. In order to reduce the leakage current of poly-Si TFTs, several offset gated structures have been reported. However, those devices, where the offset length in the source region is not same as that in the drain region, exhibit the asymmetric electrical performances such as the threshold voltage shift and the variation of the subthreshold slope. The different offset length is caused by the additional mask step for the conventional offset structures. Also the self-aligned implantation may not be applicable due to the mis-alignment problem. In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photo resistor reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate from both sides of the main gate. The poly-Si channel layer below the offset oxide is protected from the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of our new device is the offset lesion due to the offset oxide. Our experimental results show that the offset region, due to the photo resistor reflow process, has been successfully obtained in order to fabricate the offset gated poly-Si TFTs. The advantages of the proposed device are that the offset length in the source region is the same as that in the drain region because of the self-aligned implantation and the proposed device does not require any additional mask process step.