• Proceedings of the KIEE Conference
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• 1996.07a
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• pp.262-264
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• 1996

This paper presents a new dual loop control using novel vector phase locked loop(VP-PLL) for a high power static var compensator(SVC) with three-level GTO voltage source inverter(VSI). Through circuit DQ-transformation, a simple dq-axis equivalent circuit is obtained. From this, DC analysis is carried out to obtain maximum controllable phase angle ${\alpha}_{max}$ per unit current between the three phase source and the switching function of inverter, and AC open-loop transfer function is given. Because ${\alpha}_{max}$ becomes small in high power SVC, this paper proposes VP-PLL for more accurate $\alpha$-control. As a result, the overall control loop has dual loop structure, which consists of inner VP-PLL for synchronizing the phase angle with source and outer Q-loop for compensating reactive power of load. Finally, the validity of the proposed control method is verified through the experimental results.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.90-96
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• 2014

This paper presents a practical linearization technique for a wide-band bang-bang digital phase locked-loop(BBDPLL) by selecting optimal loop gains. In this paper, limitation of the theoretical design method for BBDPLL is explained, and introduced how to implement practical BBDPLLs with CMOS process. In the proposed BBDPLL, the limited cycle noise is removed by reducing the proportional gain while increasing the integer array and dither gain. Comparing to the conventional BBDPLL, the proposed one shows a small area, low power, linear characteristic. Moreover, the proposed design technique can control a loop bandwidth of the BBDPLL. Performance of the proposed BBDPLL is verified using CppSim simulator.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.55 no.1
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• pp.39-46
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• 2006

PLL is a key item of power converter for power quality compensation and power flow control. This paper proposes a novel 3-phase PLL that is composed of ALC and PI controller. The operational principle was investigated through theoretical approach, and the performance was verified through computer simulations with MATLAB and experimental works with TMS320VC33 DSP board. The proposed 3-phase PLL shows accurate performance under the voltage disturbances such as sag, harmonics. phase-angle jump, and frequency change.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.4
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• pp.356-363
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• 2004

This paper presents a precision voltage control technique of a single phase PWM inverter for a constant voltage and constant frequency(CVCF) applications. The proposed control scheme employs an additional phase-locked loop(PLL) compensator which is constructed using the output capacitor voltage and current. The computer simulation and experiment are carried out for the actual single-phase PWM inverter and it is well demonstrated from these results that the steady-state performance and total harmonic distortion(THD) are remarkably improved by employing the proposed technique.

• Proceedings of the KIEE Conference
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• 1987.11a
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• pp.86-89
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• 1987

This paper treats with the design and fabrication of a frequency synthesizer for the generation of intermediate frequency of a HF band transceiver. The synthesizer is designed to control frequencies using a phase-locked loop and it is shown that method improved the performance of frequency accuracy and locking time then that of the crystal-reference system.

• Journal of Communications and Networks
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• v.7 no.3
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• pp.248-257
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• 2005

In this paper, we develop design procedures for carrier tracking loop for orthogonal frequency division multiplexing (OFDM) systems or other systems of blocked data. In such communication systems, phase error measurements are made infrequent enough to invalidate the traditional loop design methodology which is based on analog loop design. We analyze the degradation in the OFDM schemes caused by the tracking loop and show how the performance is dependent on the rms phase error, where we distinguished between the effect of the variance in the average phase over the symbol and the effect of the phase change over the symbol. We derive the optimal tracking loop including optional delay in the loop caused by processing time. Our solution is general and includes arbitrary phase noise apd additive noise spectrums. In order to guarantee a well behaved solution, we have to check the design against margin constraints subject to uncertainties. In case the optimal loop does not meet the required margin constraints subjected to uncertainties, it is shown how to apply a method taken from control theory to find a controller. Alternatively, if we restrict the solution to first or second order loops, we give a simple loop design procedure which may be sufficient in many cases. Extensions of the method are shown for using both pilot symbols and data symbols in the OFDM receiver for phase tracking. We compare our results to other methods commonly used in OFDM receivers and we show that a large improvement can be gained.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.35-40
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• 2005

A digitally controlled phase-locked loop (DCPLL) is described. The DCPLL has basically the same structure as a conventional analog PLL except for a tracking analog-to-digital converter (ADC). The tracking ADC generates the control signal for voltage controlled oscillator. Since the DCPLL employs neither digitally controlled oscillator nor time-to-digital converter-the key building blocks of digital PLL (DPLL), there is no need for the 03de-off between jitter, power consumption and silicon area. The DCPLL was implemented in a $0.18\mu$m CMOS process and the active area is 1mm $\times$0.35 mm The DCPLL consumes S9mW during the normal opuation and $984\{mu}W$ during the power-down mode from a 1.8V supply. The DCPLL shows 16.8ps ms jitter.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.583-586
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• 2004

A typical method to control the single-phase power converter system is to utilize the zero-crossing PLL. However, this method is vulnerable to the voltage disturbance and affects the performance of controller This paper proposes a new single-phase PLL system that is composed of the adaptive linear combiner and the PI control. The operational principle was analyzed through theoretical approach and the performance was verified through simulations with MATLAB. The proposed PLL system shows rapidness and robustness in control under the voltage disturbances such as the sag, harmonics, and phase jump.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.87-90
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• 2000

This paper describes a register-controlled symmetrical delay-locked-loop (DLL) using hybrid delay line for use in a high frequency double-data-rate DRAM. The proposed DLL uses a hybrid delay line which can cover two-step delays(coarse/fine delay) by one delay element. The DLL dissipate less power than a conventional dual-loop DLL which use a coarse and a fine delay element and control separately. Additionally, this DLL not only achieves small phase resolution compared to the conventional digital DLL's when it is locked but it also has a great simple delay line compared to a complex dual-loop DLL.

• Proceedings of the KIEE Conference
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• 2005.04a
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• pp.143-145
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• 2005

A typical method to control the single-phase power converter system is to utilize the zero-crossing PLL. However, this method is vulnerable to the voltage disturbance and affects the performance of controller. This paper proposes a new single-phase PLL system that is composed of the adaptive linear combiner and the PI control. The operational principle was analyzed through theoretical approach and the performance was verified through simulations with MATLAB. The proposed PLL system shows rapidness and robustness in control under the voltage disturbances such as the sag, harmonics, and phase jump.