• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.68-76
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• 2015

Phase-change memory (PCM) is a promising technology that is anticipated to be used in the memory hierarchy of future computer systems. However, its access time is relatively slower than DRAM and it has limited endurance cycle. Due to this reason, PCM is being considered as a high-speed storage medium (like swap device) or long-latency memory. In this paper, we adopt PCM as a virtual memory swap device and present a new page replacement policy that considers the characteristics of PCM. Specifically, we aim to reduce the write traffic to PCM by considering the dirtiness of pages when making a replacement decision. The proposed replacement policy tracks the dirtiness of a page at the granularity of a sub-page and replaces the least dirty page among pages not recently used. Experimental results with various workloads show that the proposed policy reduces the amount of data written to PCM by 22.9% on average and up to 73.7% compared to CLOCK. It also extends the lifespan of PCM by 49.0% and reduces the energy consumption of PCM by 3.0% on average.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.6
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• pp.297-301
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• 2006

In the present work, we investigate the characteristics of new composition material, chalcogenide $Ge_1Se_1Te_2$ material in order to overcome the problems of conventional PRAM devices. The Tc of $Ge_1Se_1Te_2$ bulk was measured $231.503^{\circ}C$ with DSC analysis. For static DC test mode, at low voltage, two different resistances are observed. depending on the crystalline state of the phase-change resistor. In the first sweep, the as-deposited amorphous $Ge_1Se_1Te_2$ showed very high resistance. However when it reached the threshold voltage(about 11.8 V), the electrical resistance of device was drastically reduced through the formation of an electrically conducting path. The phase transition between the low conductive amorphous state and the high conductive crystal]me state was caused by the set and reset pulses respectively which fed through electrical signal. Set pulse has 4.3 V. 200 ns. then sample resistance is $80\sim100{\Omega}$. Reset pulse has 8.6 V 80 ns, then the sample resistance is $50{\sim}100K{\Omega}$. For such high resistance ratio of $R_{reset}/R_{set}$, we can expect high sensing margin reading the recorded data. We have confirmed that phase change properties of $Ge_1Se_1Te_2$ materials are closely related with the structure through the experiment of self-heating layers.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.203-204
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• 2005

PRAM (Phase change Random Access Memory) is one of the most promising candidates for next generation Non-volatile Memories. The Phase change material has been researched in the field of optical data storage media. Among the phase change materials $Ge_2Sb_2Te_5$(GST) is very well known for its high optical contrast in the state of amorphous and crystalline. However, the characteristics required in solid state memory are quite different from optical ones. In this study, the structural properties of GST thin films with composition were investigated for PRAM. The 100-nm thick GeTe and $Sb_2Te_3$ films were deposited on $SiO_2$/Si substrates by RF sputtering system. In order to characterize the crystal structure and morphology of these films, we performed x-ray diffraction (XRD) and atomic force microscopy (AFM).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.210-213
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• 2004

The phase transition between amorphous and crystalline states in chalcogenide semiconductor films can controlled by electric pulses or pulsed laser beam; hence some chalcogenide semiconductor films can be applied to electrically write/erase nonvolatile memory devices, where the low conductive amorphous state and the high conductive crystalline state are assigned to binary states. Memory switching in chalcogenides is mostly a thermal process, which involves phase transformation from amorphous to crystalline state. The nonvolatile memory cells are composed of a simple sandwich (metal/chalcogenide/metal). It was formed that the threshold voltage depends on thickness, electrode distance, annealing time and temperature, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.7-14
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• 2017

Due to the recent advances in Phage-Change Memory (PCM) technologies, a new memory hierarchy of computer systems with PCM is expected to appear. In this paper, we present a new page replacement policy that adopts PCM as a high speed swap device. As PCM has limited write endurance, our goal is to minimize the amount of data written to PCM. To do so, we defer the eviction of dirty pages in proportion to their dirtiness. However, excessive preservation of dirty pages in memory may deteriorate the page fault rate, especially when the memory capacity is not enough to accommodate full working-set pages. Thus, our policy monitors the current working-set size of the system, and controls the deferring level of dirty pages not to degrade the system performances. Simulation experiments show that the proposed policy reduces the write traffic to PCM by 160% without performance degradations.

• Transactions on Electrical and Electronic Materials
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• v.7 no.1
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• pp.7-11
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• 2006

The changes of the electrical conductivity in chalcogenide amorphous semiconductors, $Ge_{1}Se_{1}Te_{2}$, have been studied. A phase change random access memory (PRAM) device without an access transistor is successfully fabricated with the $Ge_{1}Se_{1}Te_{2}$-phase-change resistor, which has much higher electrical resistivity than $Ge_{2}Sb_{2}Te_{5}$ and its electric resistivity can be varied by the factor of $10^5$ times, relating with the degree of crystallization. 100 nm thick $Ge_{1}Se_{1}Te_{2}$ thin film was formed by vacuum deposition at $1.5{\times}10^{-5}$ Torr. The static mode switching (DC test) is tested for the $100\;{\mu}m-sized$ $Ge_{1}Se_{1}Te_{2}$ PRAM device. In the first sweep, the amorphous $Ge_{1}Se_{1}Te_{2}$ thin film showed a high resistance state at low voltage region. However, when it reached to the threshold voltage, $V_{th}$, the electrical resistance of device was drastically reduced through the formation of an electrically conducting path. The pulsed mode switching of the $20{\mu}m-sized$ $Ge_{1}Se_{1}Te_{2}$ PRAM device showed that the reset of device was done with a 80 ns-8.6 V pulse and the set of device was done with a 200 ns-4.3 V pulse.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.2
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• pp.27-32
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• 2021

This paper proposes an energy-efficient cache and memory management scheme for next-generation IoT devices. The proposed scheme adopts a low-power phase-change memory (PCM) as the main memory of IoT devices, aims at minimizing the write traffic to PCM, which is vulnerable to write operations. Specifically, when a cache block of the last-level cache memory is flushed to main memory, the cache block that causes less writes to PCM is preferentially replaced by tracking the modifications of each cache line that constitutes the cache block. In addition, by considering the reference bit of the cache block and the dirty bit of the cache lines, our scheme reduces the energy consumption without degrading the memory system performances. Through simulations using SPEC benchmarks, it is shown that the proposed scheme reduces the write traffic to PCM by 34.6% on average and the power consumption by 28.9%, without memory performance degradations.

• Proceedings of the Materials Research Society of Korea Conference
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• 2007.11a
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• pp.74.1-74.1
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• 2007

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.118-119
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• 2005

PRAM (Phase Change Random Access Memory) is well known to use reversible phase transition between amorphous (high resistance) and crystalline (low resistance) states of chalcogenide thin film by electrical Joule heating. In this paper, we introduce a stack-type PRAM device with a novel GST/TiAlN structures (GST and a heating layer of TiAlN), and report its electrical switching properties. XRD analysis result of GST thin film indicates that the crystallization of the GST film start at about $200^{\circ}C$. Electrical property results such as I-V & R-V show that the phase change switching operation between set and reset states is observed, as various input electrical sources are applied.

• The Magazine of the IEIE
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• v.33 no.5 s.264
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• pp.56-64
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• 2006