• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.1
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• pp.14-22
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• 1998

The Mathematic model of bit synchronization charge-pump Phase Locked Loop (PLL) is presented which takes into account the aperiodic reference pulses and the leakage current of the loop filter. We derive theoreitcal static phase error, overload and stability of bit synchronization charge-pump PLL using presented model and compare it with one of the conventional charge-pump PLL model. We can analysis bit synchronization charge-pump PLL exactly because our model takes into account the leakage current of the loop filter and aperiodic input data which are the charateristics of bit synchronization charge-pump PLL. We also verify it using HSPICE simulation with a bity synchronizer circuit.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.698-701
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• 2016

A phase-locked loop(PLL) with effectively increased capacitance by current modulator has been proposed. In this paper, the effective capacitance of loop filter is increased by using current modulator and it results in 1/10 reduction of capacitance in loop filter. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the same phase noise characteristic and locking time of conventional PLL.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.76-81
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• 2013

A new phase frequency detector based digital phase-locked loop (PLL) of 125 MHz was designed using the 130 nm CMOS technology library consisting of inverting edge detectors along with a typical digital phase-locked loop to reduce the lock time and jitter for mid-frequency applications. XOR based inverting edge detectors were used to obtain a transition earlier than the reference signal to change the output more quickly. The HSPICE simulator was used in a Cadence environment for simulation. The performance of the digital phase-locked loops with the proposed phase frequency detector was compared with that of conventional phase frequency detector. The PLL with the proposed detector took $0.304{\mu}s$ to lock with a maximum jitter of approximately 0.1142 ns, whereas the conventional PLL took a minimum of $2.144{\mu}s$ to lock with a maximum jitter of approximately 0.1245 ns.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.53 no.7
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• pp.365-374
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• 2004

The relay measures the frequency of the power system in order to detect faults and separate them from the system. Many estimation algorithms for the relay have been proposed to accurately measure the frequency. This paper proposes a new frequency measurement method using the digital phase locked-loop(DPLL) for the relay of the power system. The proposed method is configured with a DPLL scheme and verified through computer simulations and experimental tests. In order to cope with noises in the power system, filters are included in the input signal processing part and the frequency comparator. MATLAB is used for computer simulations and an experimental setup with a CPU and an FPGA(Field Programmable Gate Array) is constructed. The loop filter of the DPLL is run in the CPU software In adjust parameters and others are in the FPGA. Experimental tests are performed lot a function generator and the power system. Results show that the proposed method is appropriate to the frequency measurement for the relay.

• Journal of Power Electronics
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• v.15 no.1
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• pp.65-77
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• 2015

Resonant converters are well suited for induction heating (IH) applications due to their advantages such as efficiency and power density. The control systems of these appliances should provide smooth and wide power control with fewer losses. In this paper, a simple phase locked loop (PLL) based variable duty cycle (VDC) pulse density modulation (PDM) power control scheme for use in class-D inverters for IH loads is proposed. This VDC PDM control method provides a wide power control range. This control scheme also achieves stable and efficient Zero-Voltage-Switching (ZVS) operation over a wide load range. Analysis and modeling of an IH load is done to perform a time domain simulation. The design and output power analysis of a class-D inverter are done for both the conventional pulse width modulation (PWM) and the proposed PLL based VDC PDM methods. The control principles of the proposed method are described in detail. The validity of the proposed control scheme is verified through MATLAB simulations. The PLL loop maintains operation closer to the resonant frequency irrespective of variations in the load parameters. The proposed control scheme provides a linear output power variation to simplify the control logic. A prototype of the class-D inverter system is implemented to validate the simulation results.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.74-84
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• 2007

This paper presents a new dual-loop Delay Locked Loop(DLL) to expand the delay lock range of a conventional DLL. The proposed dual-loop DLL contains a Coarse_loop and a Fine_loop, and its operation utilizes one of the loops selected by comparing the initial time-difference among the reference clock and 2 internal clocks. The 2 internal clock signals are taken, respectively, at the midpoint and endpoint of a VCDL and thus are $180^{\circ}$ separated in phase. When the proposed DLL is out of the conventional lock range, the Coarse_loop is selected to push the DLL in the conventional lock range and then the Fine_loop is used to complete the locking process. Therefore, the proposed DLL is always stably locked in unless it is harmonically false-locked. Since the VCDL employed in the proposed DLL needs two control voltages to adjust the delay time, it uses TG-based inverters, instead of conventional, multi-stacked, current-starved inverters, to compose the delay line. The new VCDL provides a wider delay range than a conventional VCDL In overall, the proposed DLL demonstrates a more than 2 times wider lock range than a conventional DLL. The proposed DLL circuits have been designed, simulated and proved using 0.18um, 1.8V TSMC CMOS library and its operation frequency range is 100MHz${\sim}$1GHz. Finally, the maximum phase error of the DLL locked in at 1GHz is less than 11.2ps showing a high resolution and the simulated power consumption is 11.5mW.

• Journal of Power Electronics
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• v.16 no.1
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• pp.18-26
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• 2016

This paper proposes a compensation algorithm for reducing a specific ripple component on synchronous reference frame phase locked loop (SRF-PLL) in grid-tied single-phase inverters. In general, SRF-PLL, which is based on all-pass filter to generate virtual voltage, is widely used to estimate the grid phase angle in a single-phase system. In reality, the estimated grid phase angle might be distorted because the phase difference between actual and virtual voltages is not 90 degrees. That is, the phase error is caused by the difference between cut-off frequency of all-pass filter and grid frequency under grid frequency variation. Therefore, the effects on phase angle and output current attributed to the phase error are mathematically analyzed in this paper. In addition, the proportional resonant (PR) controller is adapted to reduce the effects of phase error. The validity of the proposed algorithm is verified through several simulations and experiments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.5
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• pp.478-491
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• 1987

In this paper, an all Digital Phase-Locked Loop(DPLL) has been propoed, which has reduced the phase error by using a half period sampling in order to improve the performance of the conventional DPLL which tracks the phase of incoming sinusoidal signal once per cycle for the Positive Going Zero crossing(PGZC) of the signal. The proposed DPLL tracks the phase of input signal twice per cycle with two samplers for the PGZC. So the loop has a half reduction of the steady state phase error fluctuation ranges without decreasing the lock-range in a whole, comparing with that of the conventional DPLL. Also, it has been known that the proposed loop is rapidly locked to input signal for the same valves of phase differenc between sucessive samples and quantization level. The analytic results of the proposed loop have been verified by computer simulation for the practically requeired conditions.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.2
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• pp.151-158
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• 2002

In this paper, Phase locked microwave oscillator having the low phase noise and high stability for digital MMDS down converter was designed. we have been analyzed the low phase noise properties by the active device nonlinear equivalent circuits and derived the necessary and sufficient conditions for high stable voltage control oscillator. And it is applied to phase locked loop, we design the phase locked microwave oscillator of frequency synthesizer. Experimental results of designed phase locked oscillator shows -85dBc/Hz @ 10KHz phase noise properties and simulation result is -90Bc/Hz @ 10kHz respectively we shows that proposed low phase noise and stable conditions of phase locked microwave oscillator can be applied to design the high stable digital MMDS frequency synthesizer.

• Transactions on Electrical and Electronic Materials
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• v.16 no.5
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• pp.241-249
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• 2015

Phase-locked-loops (PLL) have been employed in high-speed data transmission systems like wireless transceivers, disk read/write channels and high-speed interfaces. The majority of the researchers use a charge pump (CP) to obtain high performance from PLLs. This paper presents a review of various CMOS CP schemes that have been implemented for PLLs and the relationship between the CP parameters with PLL performance. The CP architecture is evaluated by its current matching, charge sharing, voltage output range, linearity and power consumption characteristics. This review shows that the CP has significant impact on the quality performance of CP PLLs.