• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.246-248
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• 2007

This paper presents fast locking PLL(Phase Locked Loop) that can improve a jitter noise characteristics and acquisition process by designing a PFD(Phase Frequency Detector) circuit. The conventional PFD has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. The advanced PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, and it has excellent performances such as 1.75us of locking time and independent duty cycle characteristic. It is fabricated in a 0.018-${\mu}m$ CMOS process, and 1.8v supply voltage, and 25MHz of input oscillator frequency, and 800MHz of output frequency and is simulated by using ADE of Cadence.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.671-674
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• 1999

In the PWM converter, PLL(Phase Locked Loop) is usually used as a tool which senses the angle of input voltage. This is sensitive to nois and needs additional hardware. In this work, we propose a sensorless control scheme of PWM converter using EKF(Extended Kalman Filter). EKF estimates a phase angle of input voltage from nonlinear state equation using measured phase currents. We control power factor and DC-link voltage utilizing the estimated phase angle. We demonstrate the effectiveness of the proposed estimation algorithm through simulations.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.320-324
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• 2011

A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked loops. A 2 GHz charge pump PLL (CPPLL) is used to justify the proposed calibration technique. The proposed digital calibration technique is implemented simply using a counter. The proposed calibration technique reduces the calibration time by up to a maximum of 50% compared other with techniques. Also by using a dual-mode CP, good current matching characteristics can be achieved to compensate $0.5{\mu}A$ current mismatch in CP. It was designed in a standard $0.13{\mu}m$ CMOS technology. The maximum calibration time is $33.6{\mu}s$ and the average power is 18.38mW with 1.5V power supply and effective area is $0.1804mm^2$.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.226-227
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• 2013

본 논문에서는 기존의 하이브리드 PLL(Phase Locked Loop) 방법에서 개선된 PLL 방법을 제시한다. 기존의 하이브리드 PLL 방법은 정상분을 동기 좌표계에서 추출하여 다시 정지 좌표계로 변환 후 제어루프를 거쳐 위상을 검출 하는 방법이다. 이를 개선하여 정지 좌표계에서 정상분을 추출하여 제어루프를 거쳐 위상을 검출 하여 기존의 하이브리드 PLL 방법에서 보다 연산 및 제어가 간소해지는 장점이 있다. 제안된 방법을 시물레이션(MATLAB Simulink)을 통해 검증하였다.

• The Transactions of the Korean Institute of Power Electronics
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• v.5 no.3
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• pp.215-220
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• 2000

본 논문에서는 SRM운전에서 맥동토오크와 부하토오크의 변화로 인한 속도변경을 줄이기 위해 동적 도통각 제어 원리를 이용한 PLL(Phase Locked Loop) 속도제어 방식을 채택하였다. SRM은 많은 장점을 가지고 있으나 토오크리플에 따른 속도변동으로 정밀한 속도제어에 어려움이 있다. SRM 구동 시스템에 PLL을 적용한 결과 전동기는 강인한 정속도 운전을 할 수 있으며, 또한 운전속도에 따라 선행각을 조정함으로서 고효율 구동을 할 수 있었다. 구성된 시스템은 운전속도와 부하의 변화에 따라 선행각이 증가함으로써 뛰어난 동적 속도제어 특성을 갖고 있으며, 인버터 인가전압을 제어하는 선행각을 조정함으로서 일정부하 영역에서 높은 효율특성을 가진다. SRM 구동 시스템의 PLL 속도제어와 고효율 구동을 위한 도통각제어를 위해 TMS320F240 DSP를 사용함으로서 디지털 제어기의 유연성과 소형화를 꾀하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.7
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• pp.23-29
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• 2012

The LC-based digitally controlled oscillator (LC-DCO), a key component of the all digital phase locked loop (ADPLL), is designed using $0.18{\mu}m$ RFCMOS process with 1.8 V supply. The NMOS core with double cross-coupled pair is chosen to realize wide tuning range, and the PMOS varactor pair that has small capacitance of a few aF and the capacitive degeneration technique to shrink the capacitive element are adopted to obtain the high frequency resolution. Also, the noise filtering technique is used to improve phase noise performance. Measurement results show the center frequency of 2.7 GHz, the tuning range of 2.5 GHz and the high frequency resolution of 2.9 kHz ~7.1 kHz. Also the fine tuning range and the current consumption of the core could be controlled by using the array of PMOS transistors using current biasing. The current consumption is between 17 mA and 26 mA at 1.8V supply voltage. The proposed DCO could be used widely in various communication system.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.7 s.337
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• pp.35-40
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• 2005

This paper proposes a fractional-N phase-locked loop (PLL) frequency synthesizer using the 3rd order ${\Delta}{\sum}$ modulator for 900MHz medium speed wireless link. The LC voltage-controlled oscillator (VCO) is used for the good phase noise property. To reduce the lock-in time, a charge pump has been developed to control the pumping current according to the frequency steps and the reference frequency is increased up to 3MHz. A 36/37 fractional-N divider is used to increase the reference frequency of the phase frequency detector (PFD) and to reduce the minimum frequency step simultaneously. A 3rd order ${\Delta}{\sum}$ modulator has been developed to reduce the fractional spur VCO, Divider by 8 Prescaler, PFD and Charge pump have been developed with 0.25um CMOS, and the fractional-N divider and the third order ${\Delta}{\sum}$ modulator have been designed with the VHDL code, and they are implemented through the FPGA board of the Xilinx Spartan2E. The measured results show that the output power of the PLL is about -lldBm and the phase noise is -77.75dBc/Hz at 100kHz offset frequency. The minimum frequency step and the maximum lock-in time are 10kHz and around 800us for the maximum frequency change of 10MHz, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.675-677
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• 2009

통신기기에서 중요한 기술 중 하나인 PLL(Phase Locked Loop) 회로는 주기적인 신호를 원하는 대로, 정확한 고정점으로 잡아주는데 그 목적을 둔다. 일반적인 구조로 위상주파수검출기(Phase Frequency detector), 루프필터(Loop filter), 전압제어발진기(Voltage Controlled Oscillator), 디바이더(Divider)로 구성되어진다. 그러나 일반적인 PLL 구조로는 지터(jitter)가 증가하고 트랙(tracking) 속도가 느리다는 단점이 있다. 이를 보완하기 위해 루프필터 전단에 차지펌프(Charge pump) 회로를 추가하여 사용하고 있다. 본 논문에서는 CMOS를 이용한 PLL용 차지펌프를 설계하였다. 설계된 회로는 $0.18{\mu}m$ CMOS 공정 기술을 사용하여 CADENCE사의 Specter로 시뮬레이션 하였으며, Virtuso2로 레이아웃 하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.61-67
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• 2009

This paper reports an Integer-N phase locked loop (PLL) frequency synthesizer which was implemented in a 250nm standard digital CMOS process for a UHF RFID wireless communication system. The main blocks of PLL have been designed including voltage controlled oscillator, phase frequency detector, and charge pump. The LC VCO has been used for a better noise property and low-power design. The source and drain juntions of PMOS transistors are used as the varactor diodes. The ADF4111 of Analog Device has been used for the external pre-scaler and N-divider to divide VCO frequency and a third order RC filter is designed for the loop filter. The measured results show that the RF output power is -13dBm with 50$\Omega$ load, the phase noise is -91.33dBc/Hz at 100KHz offset frequency, and the maximum lock-in time is less than 600us from 930MHz to 970MHz.

• Journal of Power Electronics
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• v.12 no.4
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• pp.604-614
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• 2012

This paper presents a comparative study of position sensorless control schemes based on back-electromotive force (back-EMF) estimation in permanent magnet synchronous motors (PMSM). The characteristics of the estimated back-EMF signals are analyzed using various mathematical models of a PMSM. The transfer functions of the estimators, based on the extended EMF model in the rotor reference frame, are derived to show their similarity. They are then used for the analysis of the effects of both the motor parameter variations and the voltage errors due to inverter nonlinearity on the accuracy of the back-EMF estimation. The differences between a phase-locked-loop (PLL) type estimator and a Luenberger observer type estimator, generally used for extracting rotor speed and position information from estimated back-EMF signals, are also examined. An experimental study with a 250-W interior-permanent-magnet machine has been performed to validate the analyses.