• Journal of Electrical Engineering and Technology
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• 제10권4호
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.607-608
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• 2006

A CMOS phase-locked loop (PLL) which synthesizes frequencies between $6.336{\sim}8.976GHz$ in steps of 528MHz and settles in approximately 150ns using the 528MHz reference clock is presented. Frequency hopping between the bands in the each mode is critical point to design the PLL in multi-band orthogonal frequency division multiplexing (OFDM) because frequency switching between each band is less than 9.5ns. To achieve the fast loop settling, integer-N PLL that operates with the high reference frequency to meet the settling requirement is implemented. Two PLLs that operate at 9GHz and 528MHz is integrated and shows the band hopping lower than 1ns.

• 조명전기설비학회논문지
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• 제29권10호
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• pp.73-82
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• 2015

This paper proposes an ripple reduction algorithm and analyzes the effects of offset and scale errors generated by voltage sensor while measuring grid voltage in grid-tied single-phase inverters. Generally, the grid-connected inverter needs to detect the phase angle information by measuring grid voltage for synchronization, so that the single-phase inverter can be accurately driven based on estimated phase angle information. However, offset and scale errors are inevitably generated owing to the non-linear characteristics of voltage sensor and these errors affect that the phase angle includes 1st harmonic component under using SRF-PLL(Synchronous Reference Frame - Phase Locked Loop) system for detecting grid phase angle. Also, the performance of the overall system is degraded from the distorted phase angle including the specific harmonic component. As a result, in this paper, offset and scale error due to the voltage sensor in single-phase grid connected inverter under SRF-PLL is analyzed in detail and proportional resonant controller is used to reduce the ripples caused by the offset error. Especially, the integrator output of PI(Proportional Integral) controller in SRF-PLL is selected as an input signal of the proportional resonant controller. Simulation and experiment are performed to verify the effectiveness of the proposed algorithm.

• 전력전자학회논문지
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• 제18권3호
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• pp.205-210
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• 2013

This paper presents a novel hall sensor fault detection and fault-tolerant control method for a high-speed permanent magnet synchronous motor (PMSM) drive system. A phase locked loop (PLL) type position estimator is used with a conventional interpolation based rotor position estimator to reduce position errors due to misalignment of hall sensors. The expected trigger time of hall sensor's output is used for detecting hall sensor fault condition and the PLL type position estimator is reconfigured for fault-tolerant control at the hall sensor fault condition. The proposed method can minimize current ripples during the transition from sensored control using hall sensors to sensorless control. Experimental results have been proposed to prove the validity of the proposed method.

• 제어로봇시스템학회논문지
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• 제15권3호
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• pp.258-264
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• 2009

This paper presents two control algorithms for the frequency and amplitude of the resonator of a micro sensor. One algorithm excites the resonator at its a priori unknown resonant frequency, and the other algorithm alters the resonator dynamics to place the resonant frequency at a fixed frequency, chosen by the designer. Both algorithms maintain a specified amplitude of oscillations. The control system behavior is analyzed using an averaging method, and a quantitative criterion is provided for the selecting the control gain to achieve stability. Tracking and estimation accuracy of the natural frequency under the presence of measurement noise is also analyzed. The proposed control algorithms are applied to the MEMS dual-mass gyroscope without mechanical connecting beam between two proof-masses. Simulation results show the effectiveness of the proposed control algorithms which guarantee the proof-masses of the gyroscope to move in opposite directions with the same resonant frequency and oscillation amplitude.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 V
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• pp.2485-2488
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• 2003

본 논문에서는 DSP를 이용하여 운동하는 물체의 회전량을 측정하는 실린더형 진동 자이로스코프(이하 자이로) 제어기를 개발하였다. 진동 자이로를 구동하기 위해서는 정밀 진동제어와 신호 처리와 같은 고급 제어 기술이 필요하다. 정밀진동제어는 진동 자이로를 구동하기 위해 필요한 핵심기술로써 기존의 PLL(phase-locked loop)방식은 외부환경에 민감하여 구현이 까다로울 뿐만 아니라 자이로 개개의 고유 진동수가 다르기 때문에 대량 생산에 어려움이 있었다. 또한 자이로 출력 신호로부터 회전량을 검출하기 위해서는 진폭과 당향성 검출의 본 회로뿐만 아니라 잡음 제거와 신호 증폭, 온도 보상과 같은 전처리 과정도 필요하다. 본 논문에서는 DSP를 통해 정밀 진동제어와 잡음 제거, 방향성 검출 등의 기능들을 구현하였으며 증폭과 진폭(회전량) 검출은 아날로그 회로를 이용하였다. 또 한 외부와의 인터페이스를 위해 D/A 회로를 설계하였고 이들을 실험을 통해 검증하였다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2011년도 추계학술대회
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• pp.271-272
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• 2011

본 논문은 SOGI를 이용한 정상분 전압 검출을 기반으로 하는 SRF(synchronous reference frame)-PLL(phase locked loop) 시스템을 제안한다. 일반화된 2차 적분기의 이중으로 사용하여 QSG(Quadrature-signals generator)의 성능을 개선하여 전압 불평형, 고조파 왜곡 등으로 인한 오차 발생 시에도 빠르고 정확한 위상 검출이 가능하도록 하였으며 본 논문에서 제시한 알고리즘은 PSIM 프로그램 결과를 통하여 타당성을 입증한다.

• 전기학회논문지
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• 제59권4호
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• pp.793-796
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• 2010

The equalizer compensates a signal distorted by transmission lines and amplifying stages, so the signal can have uniform characteristics over all frequency range. The equalizer in ODD(Optical Disc Drive) improves the stability of the extracted clock from a received signal and the readability of an inserted disc by suppressing noise and ISI(Inter-Symbol Inference). The length of marks-spaces and track pitch on discs becomes shorter as the recording density of an optical media is higher, which causes noise and ISI. And, the sensitivity about the fluctuation of physical systems is higher as the optical devices become more complicate. This paper proposes a method to select the coefficient of built-in equalizer of ODD in order to maintain the quality of signals against noise and ISI caused by system fluctuation.

• 대한전자공학회논문지
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• 제20권2호
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• pp.23-28
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• 1983

본 논문에서는 위상 고정 회로를 이용한 직류 전동기의 동기화 속도 제어 방법 중 가변 순차 여파기를 주파수 비교기로 사용한 제어 방식을 제안하고, 이를 실제로 구성하여 특성을 조사하였다. 가변 순차 여파기를 이용하므로써 제어계의 과도 응답 시간을 단순한 가역 계수기를 주파수 비교기로 이용한 계보다 15(%) 이상 개선시켰고, 정상 상태 속도 오차는 1회전상 0.05(%)이내로 줄일 수 있었다.

• 전기전자학회논문지
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• 제15권2호
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• pp.129-133
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• 2011

A spread spectrum clock generation is an efficient way to reduce electro-magnetic interference (EMI) radiation in modern mixed signal chip systems. The proposed circuit generates the spread spectrum clock by directly injecting the modulation voltage into the voltage-controlled oscillator (VCO) current source for SATA II. The resulting 33KHz modulation profile has a Hersey-Kiss shape with a rounded peak. The chip has been fabricated using $0.18{\mu}m$ CMOS process and test results show that the proposed circuit achieves 0.509% (5090ppm) down spreading at 1.5GHz and peak power reduction of 10dB. The active chip area is 0.36mm ${\times}$ 0.49mm and the chip consumes 30mW power at 1.5GHz.