• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.18 no.5 s.120
• /
• pp.511-521
• /
• 2007

In this paper, we designed and fabricated a Ka-band synthesizer module. In addition, the systematic layout procedure and the test procedure were presented for the construction of compact synthesizer. To implement the Ka-band synthesizer, X-band VCO is employed as VCO and its frequency was multiplied by 3 with frequency tripler. The fabricated frequency synthesizer shows a frequency tuning range of 500 MHz, output power of about 14 dBm, and a phase noise of -96.17 dBc/Hz at the 100 kHz offset frequency.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.60 no.2
• /
• pp.451-454
• /
• 2011

In this paper, a wideband clock generator using novel Automatic frequency calibration(AFC) scheme is proposed. Wideband clock generator using AFC has the advantage of small VCO gain and wide frequency band. The conventional AFC compares whether the feedback frequency is faster or slower then the reference frequency. However, the proposed AFC can detect frequency difference between reference frequency with feedback frequency. So it can be reduced an operation time than conventional methods AFC. Conventional AFC goes to the initial code if the frequency step changed. This AFC, on the other hand, can a prior state code so it can approach a fast operation. In simulation results, the proposed clock generator is designed for DisplayPort using the CMOS ring-VCO. The VCO tuning range is 350MHz, and a VCO frequency is 270MHz. The lock time of clock generator is less then 3us at input reference frequency, 67.5MHz. The phase noise is -109dBC/Hz at 1MHz offset from the center frequency. and power consumption is 10.1mW at 1.8V supply and layout area is $0.384mm^2$.

• 한국정보통신설비학회:학술대회논문집
• /
• 2005.08a
• /
• pp.159-165
• /
• 2005

The proposed optical transmitter is composed of FF(flip flop) , PLL (phase locked loop), reference clock generator, serializer and LD driver 10x250 Mb/s data arrays are translated to the 2.5 Gb/s data signal by serializer. In this case, 1 data bus is allocated usually as a reference clock for synchronization. In this proposed optical transmitter, 125 MHz reference clock is generated from 10x250 Mb/s data arrays by reference clock generator. From this method. absent of reference clock bus is available and more data transmission become possible. To achieve high speed operation, the serializer circuit is designed as two stacks. For 10:1 serialization, 10 clocks that have 1/10 lambda differences is essential, so the VCO (voltage controlled oscillator) composed of 10 delay buffers is designed. PLL is for runing at 250 MHz, and dual PFD(phase frequency detector) is adopted for fast locking time. The optical transmitter is designed by using 0.35 um CMOS technology.

• Journal of Power Electronics
• /
• v.11 no.5
• /
• pp.632-638
• /
• 2011

This paper presents a cascaded coil flux control based on a Current Source Parallel Resonant Push-Pull Inverter (CSPRPI) for Induction Heating (IH) applications. The most important problems associated with current source parallel resonant inverters are start-up problems and the variable response of IH systems under load variations. This paper proposes a simple cascaded control method to increase an IH system's robustness to load variations. The proposed IH has been analyzed in both the steady state and the transient state. Based on this method, the resonant frequency is tracked using Phase Locked Loop (PLL) circuits using a Multiplier Phase Detector (MPD) to achieve ZVS under the transient condition. A laboratory prototype was built with an operating frequency of 57-59 kHz and a rated power of 300 W. Simulation and experimental results verify the validity of the proposed power control method and the PLL dynamics.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.63 no.10
• /
• pp.1467-1472
• /
• 2014

This paper study on powering characteristic on speed variation of propulsion system of prototype 8200 electric locomotive propulsion system through simulation modeling. For this purpose, it being applied in the field of railway IGBT (Insulated Gate Bipolar Transistor) elements are used. Converter was performed PLL (Phase-Locked Loop) control method that is used to control the phase and output voltage, and the inverter was carried an indirect vector control method to control the speed of traction motor. The results of simulation by modeling and experimental unit, we was confirmed that converter is controlled a unity power factor and output voltage by reference voltage. Also traction motor was controlled by indirect vector control and SVPWM inverter switching method very well.

• Journal of Power Electronics
• /
• v.7 no.2
• /
• pp.97-108
• /
• 2007

This paper describes simple control structures for a vector controlled stand-alone induction generator (IG) for use under variable speeds. Different control principles, indirect vector control and deadbeat current control, are developed for a voltage source PWM converter and the three-phase variable speed squirrel-cage IG to regulate DC-link and generator voltages with a newly designed phase locked loop circuit. The required reactive power for the variable speed IG is supplied by means of a PWM converter and a capacitor bank to buildup the voltage of the IG without the need for a battery, to reduce the rating of the PWM converter while using only three sensors and to eliminate the harmonics generated by the PWM converter. These proposed schemes can be used efficiently for variable speed wind energy conversion systems. The measurements of the IG systems at various speeds and loads are given and show that these systems are capable of good AC and DC voltage regulation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.16 no.10 s.101
• /
• pp.1043-1049
• /
• 2005

In OFDM system suitable for high capacity high speed broadband transmission, ICI caused by phase noise degrades system performance seriously by destroying the orthogonality among subcarriers. In this paper, a new STFBC method combining ICI self cancellation scheme and antenna, time, frequency diversity is studied to reduce ICI effectively. CPE and ICI are analyzed by the phase noise linear approximation method in the proposed STFBC OFDM system. CIR, PICR and BER are discussed to compare the system performance degraded by phase noise of PLL. As results, STFBC method significantly reduces ICI. Furthermore, the SCI that usually happens in the traditional STBC, SFBC diversity coding method can be easily avoided.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.9
• /
• pp.74-80
• /
• 2009

This paper describes a $2{\sim}6GHz$ CMOS frequency synthesizer that employs only one LC-tank voltage controlled oscillator (VCO). For wide-band operation, optimized LO signal generator is used. The LC-tank VCO oscillating in $6{\sim}8GHz$ provides the required LO frequency by dividing and mixing the VCO output clocks appropriately. The frequency synthesizer is based on a fractional-N phase locked loop (PLL) employing third-order 1-1-1 MASH type sigma-delta modulator. Implemented in a $0.18{\mu}m$ CMOS technology, the frequency synthesizer occupies the area of $0.92mm^2$ with of-chip loop filter and consumes 36mW from a 1.8V supply. The PLL is completed in less than $8{\mu}s$. The phase noise is -110dBC/Hz at 1MHz offset from the carrier.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.11
• /
• pp.9-16
• /
• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.12A
• /
• pp.2000-2011
• /
• 2001

In this Paper, we convert conventional low speed(1x, 6x) DVD systems designed by analog PLL(Phase Locked Loop) into digital PLL to operate at high speed systems flexibly, and present optimal DPLL model in high speed(20x) DVD systems. Especially, we focused on the design of DPLL that can overcome channel effects such as bulk delay, sampling clock frequency offset and asymmetry phenomenon in high speed DVD systems. First, the modified Early-Late timing error detector as digital timing recovery scheme is proposed. And the four-sampled compensation algorithm using zero crossing point as asymmetry compensator is designed to achieve high speed operation and strong reliability. We show that the proposed timing recovery algorithm provides enhanced performances in jitter valiance and SNR margin by 4 times and 3dB respectively. Also, the new four-sampled zero crossing asymmetry compensation algorithm provides 34% improvement of jitter performance, 50% reduction of compensation time and 2.0dB gain of SNR compared with other algorithms. Finally, the proposed systems combined with asymmetry compensator and DPLL are shown to provide improved performance of about 0.4dB, 2dB over the existing schemes by BER evaluation.