• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1252-1258
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• 1999

This paper describes a COMS IF transceiver IC for 10-MHz bandwidth wireless local loops. It interfaces between the RF section and the digital MODEM section and performs the IF-to-baseband (Rx) and baseband-to-IF (Tx) frequency conversions. The chip incorporates variable gain amplifiers, phase-locked loops, low pass filters, analog-to-digital and digital-to-analog converters. It has been implemented in a 0.6 -${\mu}{\textrm}{m}$ 2-poly 3-metal CMOS process. The phase-locked loops include voltage-controlled oscillators, dividers, phase detectors, and charge pumps on chip. The only external complonents are the filter and the varactor-tuned LC tank circuit. The chip size is 4 mm $\times$ 4 mm and the total supply current is about 57 mA at 3.3 V.

• Journal of IKEEE
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• v.27 no.4
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• pp.573-578
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• 2023

This paper introduces a new locking technique applicable to high-performance digital Phase-Locked Loops (DPLL). The study employs additional thermometer codes to reduce quantization errors in LC-based Digital Controlled Oscillators (DCO). Despite not implementing the entire DCO codes in thermometer mode, this method effectively reduces quantization errors through enhanced linearity. In the initial locking phase, binary codes are used, and upon completion of locking, the system transitions to thermometer codes, achieving high frequency linearity and reduced jitter characteristics. This approach significantly reduces the number of switches required and minimizes the oscillator's area, especially in applications requiring low DCO gain (Kdco), compared to the traditional method that uses only thermometer codes. Furthermore, the jitter performance is maintained at a level equivalent to that of the thermometer-only approach. The efficacy of this technique has been validated through modeling and design at the RTL level using SystemVerilog and Verilog HDL.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.2
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• pp.339-344
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• 2017

A novel structure of phase locked loop (PLL) which has small size and fast locking time with Early-late detector, Duty-rate modulator, and Lock status indicator (LSI) is proposed in this paper. The area of loop filter usually occupying the larger portion of the chip is minimized using a single small capacitor. While the conventional PLL with a single capacitor loop filter cannot work stably, the proposed PLL with two charge pumps works stably because the output voltage waveform of the proposed a single capacitor loop filter is the same as the output voltage waveform of the conventional 2nd-order loop filter. The two charge pumps are controlled by the Early-late detector which detects early-late status of UP and DN signals, and Duty-rate modulator which generates a steady duty-rate signal. Fast locking time is achieved using LSI. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.4
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• pp.199-204
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• 2010

Recently, the transmission amount of information that each single person requires is growing by development of electron information communication technology. So in this paper we analysis the phase noise characteristics to obtain a most suitable of SNR performance request characteristic by BER on CATV transmission system that satisfy performance request DOCSIS 2.0 standard. Especially we get the parameter value of PLL that satisfy phase noise characteristic request standard using developed simulator. Presented method can be used to obtain a performance request standard connection performance request standard of high speed CATV transmission system in the future.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.9
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• pp.1315-1322
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• 2015

This paper proposes an active islanding detection method for the BESS (Battery Energy Storage System) with 3-phase inverter which is connected to the AC grid. The proposed method adopts the DDSRF (Decoupled Double Synchronous Reference Frame) PLL (Phase Locked-Loop) so that the independent control of positive-sequence and negative-sequence current is successfully carried out using the detected phase angle information. The islanding state can be detected by sensing the variation of negative-sequence voltage at the PCC (Point of Common Connection) due to the injection of 2-3% negative-sequence current from the BESS. The proposed method provides a secure and rapid detection under the variation of negative-sequence voltage due to the sag and swell. The feasibility of proposed method was verified by computer simulations with PSCAD/EMTDC and experimental analyses with 5kW hardware prototype for the benchmark circuit of islanding detection suggested by IEEE 1547 and UL1741. The proposed method would be applicable for the secure detection of islanding state in the grid-tied Microgrid.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.7
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• pp.1005-1011
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• 2015

This paper proposes the DC offset compensation algorithm with fast response to the sensed grid voltage in the single-phase grid connected inverter. If the sensor of the grid voltage has problems, the DC offset of the grid voltage can be generated. This error must be resolved because the DC offset can generate the estimated grid frequency error of the phase-locked loop (PLL). In conventional algorithm to compensate the DC offset, the DC offset is estimated by integrating the synchronous reference frame d-axis voltage during one period of the grid voltage. The conventional algorithm has a drawback that is a slow dynamic response because monitoring the one period of the grid voltage is required. the proposed algorithm has fast dynamic response because the DC offset is consecutively estimated by transforming the d-axis voltage to synchronous reference frame without monitoring one cycle time of the grid voltage. The proposed algorithm is verified from PSIM simulation and the experiment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.4
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• pp.338-347
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• 1989

In this paper, the digital frequency synthesizer with the clock ccunting method is designed and implemented to increase the performace of the digital frequency synthesizer with pahse accumulating method which was developed before. Unlike an phase accumulating method, clock countind method is supplied a continually changeable clock frequency with PLL(Phase Locked Loop) and allocated a fixed phase step with N-ary counter. Form the experimenta results, it is confirmed that any periodic distorition phenomena are disappeared, and truncation harmonics are more reduced. But the output bandwidths are decreased in inverse proportion to the counter counting number and the circuits are somewhat complex than phase accumulating method.

• The Transactions of the Korean Institute of Power Electronics
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• v.8 no.6
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• pp.543-550
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• 2003

Thin paper proposes a new three-phase rectifier that actively shapes the input current sinusoidal by means of two rectifier bridges, each followed by a dc-dc boost converter. The proposed approach draws sinusoidal input current at unity power factor and has output voltage regulation capability The size and weight of magnetic material Is reduced by Incorporating a low KVA three-phase autotransformer and by directly connecting the dc outputs each other without using low frequency interphase transformer(IPT). The operation principle is described along with simple control method, and experimental results on a 1.5KW prototype are provided.

• Journal of Satellite, Information and Communications
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• v.5 no.1
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• pp.1-5
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• 2010

Recently, the transmission amount of information that each single person requires is growing by development of electron information communication technology. So in this paper we analysis the phase noise characteristics to obtain a most suitable of SNR performance request characteristic by BER on CATV transmission system that satisfy performance request DOCSIS 2.0 standard. Especially we get the parameter value of PLL that satisfy phase noise characteristic request standard using developed simulator. Presented method can be used to obtain a performance request standard connection performance request standard of high speed CATV transmission system in the future.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.7
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• pp.704-712
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• 2016

Recently, the installation of photovoltaic (PV) systems has been increasing due to the worldwide interest in eco-friendly and infinitely abundant solar energy. However, the output power of PV systems is highly influenced by the surrounding environment. For instance, a string of PV systems composed of modules in series may become inoperable under cloudy conditions or when in the shade of a building. In other words, under these conditions, the existing control method of PV systems does not allow the string to be operated in the normal way, because its output voltage is lower than the operating range of the grid connected inverter. In order to overcome this problem, we propose a new control method using a DC-DC voltage regulator which can compensate for the voltage of each string in the PV system. Also, based on the PSIM S/W, we model the DC-DC voltage regulator with constant voltage control & MPPT (Maximum Power Point Tracking) control functions and 3-Phase grid connected inverter with PLL (Phase-Locked Loop) control function. From the simulation results, it is confirmed that the present control method can improve the operating efficiency of PV systems by compensating for the fluctuation of the voltage of the strings caused by the surrounding conditions.