• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.5
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• pp.13-18
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• 1978

A delay switching PLL (DSPLL) is proposed for improvement of the frequency acquisition Performance (pull-in range) while keeping a narrow bandwidth LPF. It has, between the phase detector and the LPF, just a simple RC delay circuit, a switch and another phase detector controlling the switching time. For the common second order PLL, the pull-in capability of the DSPLL is analyzed approximately, without considering additive white noise effect, and verified experimentally. It is shown that the delay switching extends the pull-in range significantly, as much as a half of lock-range. At the phase tracking mode, the delay switching does not function, to make the DSPLL be a normal PLL.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05a
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• pp.28-31
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• 2004

A Quadrature phase detector for high-speed delay-locked loop is introduced. The proposed Quadrature phase detector is composed of two nor gates and it determines if the phase difference of two input clocks is 90 degrees or not. The delay locked loop circuit including the Quadrature phase detector is fabricated in a 0.18 urn standard CMOS process and it operates at 5 ㎓ frequency. The phase error of the delay-locked loop is maximum 2 degrees and the circuits are robust with voltage, temperature variations.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.76-81
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• 2013

A new phase frequency detector based digital phase-locked loop (PLL) of 125 MHz was designed using the 130 nm CMOS technology library consisting of inverting edge detectors along with a typical digital phase-locked loop to reduce the lock time and jitter for mid-frequency applications. XOR based inverting edge detectors were used to obtain a transition earlier than the reference signal to change the output more quickly. The HSPICE simulator was used in a Cadence environment for simulation. The performance of the digital phase-locked loops with the proposed phase frequency detector was compared with that of conventional phase frequency detector. The PLL with the proposed detector took $0.304{\mu}s$ to lock with a maximum jitter of approximately 0.1142 ns, whereas the conventional PLL took a minimum of $2.144{\mu}s$ to lock with a maximum jitter of approximately 0.1245 ns.

• Journal of Multimedia Information System
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• v.5 no.3
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• pp.155-162
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• 2018

Nowadays, the tracking technology of Quadrant Detector will become actual by new micro devices. Based on the past filed data of the reception experiment with COMETS satellite, we have studied on new device (AD8302, phase difference detector) was acquired and suspect its abilities. In 1998, we have developed a Quadrant Detector for mobile to track a weak signal from satellite on Ka band of COMETS. The Quadrant Detector is comprised of four dedicated feed components for reception under an environment of Nakagami - Rician fading, and one transmission and reception feed component. We were successful in receiving a 23 GHz beacon signal from ICE transponder of the COMETS and succeeded in tracking the satellite from a moving vehicle at speeds of approximately 10 ~ 20 Km/h on paved roads. In 2018, with new device AD8302, we have verified new QD system and performed a simulation, based on the past filed experiment. This new device shall be improving the tracking abilities from mobile body on the earth to the multimedia satellite.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.7
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• pp.540-549
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• 2017

A phase frequency detector(PFD) composed of logic circuits is widely used in a phase locked loop(PLL) due to the easy implementation for integrated circuits. A frequency locked loop(FLL) removes the reference oscillator in the PLL, and the resonator serves as a reference oscillator. A frequency detector(FD) is indispensable for the FLL configuration, and a FD, which is usually composed of a mixer is used to build an FLL. In this paper, instead of FD using mixer, a FD is constructed by using 1.175 GHz resonator composed of microstrip and PFD taking the versatility of PFD into consideration. Using the designed FD, FLL oscillating at a frequency of 1.175 GHz is composed. As a result of comparison with the FLL composed of FD using mixer, it was confirmed that the proposed FLL has better phase noise performance than FLL using mixer FD with FLL bandwidth.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.10
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• pp.1147-1158
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• 2008

In this paper, we designed a phase-looking circuit that locks the 16.8 GHz VTDRO to a 700 MHz SAW oscillator using SPD as a phase detector Direct phase locking with loop filter alone causes the problem of lock time, so VTDRO is phase leered by loop filter with the aid of time varying square wave current generator. The current generator is related to the loop filter and needs the systematic toning. In this paper, a systematic design of the current generator and loop filter is presented. The fabricated PLDRO shows a stabilized frequency of 16.8 GHz, a output power 6.3 dBm, and a phase noise of -101 dBc/Hz at the 100 kHz offset.

• Journal of the Society of Cosmetic Scientists of Korea
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• v.23 no.3
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• pp.161-167
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• 1997

Determination of several cationic surfactants in cosmetics has been investigated. Reverse phase ion pair chromatography was used to identify and quantitate cationic surfactants. Cationic surfactants analyzed in this experiment were cetylpyridium chloride, stearyltrimetylammonium chloride, bezalkonium chloride, benzyldicethylcetylammonium chloride, and bihenyltrimethyl ammonium chloride. The separation was achieved on a reverse phase coumn with 10mM HCl-acetonitrile eluent. In this condition, the most of cationic surfactants with exception of CPC and CTAC respectively with suppressed conductivity detector and UV detector connected in series. The calibration curves obtained by plotting the peak areas of the cationic surfactants were linear at levels ranging from 0.005 to 0.1% correlation coefficient, r=0.9988. The detection limits were 1 to 5ppm in sample solution. The average recoveries of cationic surfactants added to hair treatment cream and hair rinse in three to five experiments were 96.7 105.2% and relative standard deviations were 1.1-3.8%. The case that there were CPC and CTAC in same solution was also tested. CPC and CTAC which couldn't be separated on reverse phase column were quantitated with suppressed conductivity detector and UV detector connected in series. Recovery of CPC and CTAC were 101.6 and 89.2% respectively. The proposed method was applied to the determination of cationic surfactants in commercial hair treatment cream.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.385-388
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• 2003

In this paper, a D-Latch is replaced by a memory cell on the proposed PFD to improve response tine by reducing reset me. The PFD has been simulated using HSPICE with a Hynix 0.35um CMOS process to prove the performance improvement.

• Journal of information and communication convergence engineering
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• v.9 no.3
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• pp.305-309
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• 2011

This paper proposes a new rotational frequency detector (RFD) for phase-locked loop (PLL) or clock and data recovery (CDR) applications for fast frequency acquisition. The proposed RFD uses the four states finite state machine (FSM) model to accelerate the frequency acquisition time. It is modeled and simulated with MATLAB Simulink. The functionalities of the proposed RFD are examined and the results are compared to those of a conventional RFD. The proposed RFD's frequency acquisition time is four times faster than that of a conventional one. The proposed RFD incorporated with a phase detector (PD) in PLL or CDR is expected to improve the frequency and phase acquisition performance later greatly.

• ETRI Journal
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• v.35 no.2
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• pp.218-225
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• 2013

The pull-out frequency of a second-order phase lock loop (PLL) is an important parameter that quantifies the loop's ability to stay frequency locked under abrupt changes in the reference input frequency. In most cases, this must be determined numerically or approximated using asymptotic techniques, both of which require special knowledge, skills, and tools. An approximating formula is derived analytically for computing the pull-out frequency for a second-order Type II PLL that employs a sinusoidal characteristic phase detector. The pull-out frequency of such PLLs can be easily approximated to satisfactory accuracy with this formula using a modern scientific calculator.