• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.34 no.4
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• pp.251-255
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• 2021

a-Si is commonly considered as a primary candidate for the formation of passivation layer in heterojunction (HIT) solar cells. However, there are some problems when using this material such as significant losses due to recombination and parasitic absorption. To reduce these problems, a wide bandgap material is needed. A wide bandgap has a positive influence on effective transmittance, reduction of the parasitic absorption, and prevention of unnecessary epitaxial growth. In this paper, the adoption of a-SiO_x:H as the intrinsic layer was discussed. To increase lifetime and conductivity, oxygen concentration control is crucial because it is correlated with the thickness, bonding defect, interface density (D_it), and band offset. A thick oxygen-rich layer causes the lifetime and the implied open-circuit voltage to drop. Furthermore the thicker the layer gets, the more free hydrogen atoms are etched in thin films, which worsens the passivation quality and the efficiency of solar cells. Previous studies revealed that the lifetime and the implied voltage decreased when the a-SiOx thickness went beyond around 9 nm. In addition to this, oxygen acted as a defect in the intrinsic layer. The D_it increased up to an oxygen rate on the order of 8%. Beyond 8%, the D_it was constant. By controlling the oxygen concentration properly and achieving a thin layer, high-efficiency HIT solar cells can be fabricated.

• Journal of the Korean Society of Industry Convergence
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• v.7 no.3
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• pp.259-263
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• 2004

In the manufacture progress of LCD or semiconductor, there are used many kinds of gas like erosion gas, dilution gas, toxic gas as a progress which used these gas there are required high puritize to increase accumulation rate of semiconductor or LCD materials work progress of semiconductor or LCD it demand many things like the material which could minimize metallic dust that could be occured by reaction between gas and transfer pipe laying material, illumination of the surface, emition of the gas, metal liquation, welding etc also demand quality geting stricted. Material-Low-sulfur-contend (0.007-0010), vacuum-arc-remelt(VAR), seamless, high-purity tubing material is recommend for enhance welding lower surface defect density All wetted stainless steel surface must be 316LSS elecrto polishinged with ${\leq}0.254{\mu}m$($10.0{\mu}in$) Ra average surface finish, $Cr/Fe{\geq}1.1$ and $Cr_2O_3$ thickness ${\geq}25{\AA}$ From the AES analytical the oxide layer thickness (23.5~36 angstroms silicon dioxide equivalent) and chromum to iron ratios is similar to those generally found on electropolished stainless steel., molybdenum and silicon contaminants ; elements characteristic of stainless steel (iron, nickel and chromium); and oxygen were found on the surface Phosphorus and nitrogen are common contaminants from the electropolish and passivation steps.

• Current Photovoltaic Research
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• v.11 no.2
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• pp.44-48
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• 2023

In heterojunction technology (HJT) solar cells, low-temperature curing paste is used because the passivation layer deteriorates at high temperatures of 200℃ or higher. However, manufacturing HJT photovoltaic (PV) modules is challenging due to the weak peel strength between busbar electrodes and cells after soldering process. For this issue, the electrode thicknesses of the busbars of the HJT solar cell were analyzed, and the peel strengths between electrodes and wires were measured after soldering using an infrared (IR) lamp. As a result, the electrodes printed by the screen printing method had a difference in thickness due to screen mask. Also, as the thickness of the electrode increased, the peel strength of the wire increased.

• Journal of the Korean institute of surface engineering
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• v.33 no.2
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• pp.93-100
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• 2000

Effects of Ti content and Ti underlayer on the pitting behavior of TiN coated AISI 304 stainless steel have been studied. The stainless steel containing 0.1~1.0wt% Ti were melted with a vacuum melting furnace and heat treated at $1050^{\circ}C$ for 1hr for solutionization. The specimen were coated with l$\mu\textrm{m}$ and 2$\mu\textrm{m}$ thickness of Ti and TiN by E-beam PVD method. The microstructure and phase analysis were conducted by using XRD, XPS and SEM with these specimen. XRD patterns shows that in TiN single-layer only the TiN (111) Peak is major and the other peaks are very weak, but in Ti/TiN double-layer TiN (220) and TiN (200) peaks are developed. It is observed that the surface of coating is covered with titanium oxide (TiO$_2$) and titanium oxynitride ($TiO_2$N) as well as TiN. Corrosion potential on the anodic polarization curve measured in HCl solution increase in proportion to the Ti content of substrate and by a presence of the Ti underlayer, whereas corrosion and passivation current densities are not affected by either of them. The number and size of pits decrease with increasing Ti content and a presence of the coated Ti film as underlayer in the TiN coated stainless steel.

• Journal of the Korean Society for Precision Engineering
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• v.20 no.5
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• pp.218-224
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• 2003

This paper describes a novel MEMS integration technique on a CMOS chip. MEMS integration on CMOS circuit has many advantages in view of manufacturing cost and reliability. The surface topography of a CMOS chip from a commercial foundry has 0.9 ${\mu}{\textrm}{m}$ bumps due to the conformal coating on aluminum interconnect patterns, which are used for addressing each MEMS element individually. Therefore, it is necessary to achieve a flat mirror-like CMOS chip fer the microelectromechanical system (MEMS) such as micro mirror array. Such CMOS chip needs an additional thickness of the dielectric passivation layer to ease the subsequent planarization process. To overcome a temperature limit from the aluminum thermal degradation, this study uses RF sputtering of silicon nitride at low temperature and then polishes the CMOS chip together with the surrounding dummy pieces to define a polishing plane. Planarization reduces 0.9 ${\mu}{\textrm}{m}$ of the bumps to less than 25 nm.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.57-58
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• 2006

In MIM (metal insulator metal) capacitor, Ru (ruthenium) has been suggested as new bottom electrode due to its excellent electrical performance, a low leakage of current and compatibility to the high dielectric constant materials. In this case of Ru bottom electrode, CMP (chemical mechanical planarization) process was needed m order to planarize and isolate the bottom electrode. In this study, the effect of chemical A on polishing and etching behavior was investigated as functions of chemical A concentration, abrasive particle and pressure. Chemical A was used as oxidant and etchant. The thickness of passivation layer on the treated Ru surface increased with the increase of chemical A concentration. The etch rate and removal rate of Ru were increased by the addition of chemical A. The removal rate was highest m slurry of pH 9 with the addition of 0.1 M chemical A and 2 wt% alumina at 4 psi. The maximum removal rate is about 80 nm/min.

• International Journal of Internet, Broadcasting and Communication
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• v.12 no.2
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• pp.30-36
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• 2020

We demonstrated a successful fabrication of 4" Gallium Nitride (GaN)/Diamond High Electron Mobility Transistors (HEMTs) incorporated with Inner Slot Via Hole process. We made in manufacturing technology of 4" GaN/Diamond HEMT wafers in a compound semiconductor foundry since reported [1]. Wafer thickness uniformity and wafer flatness of starting GaN/Diamond wafers have improved greatly, which contributed to improved processing yield. By optimizing Laser drilling techniques, we successfully demonstrated a through-substrate-via process, which is last hurdle in GaN/Diamond manufacturing technology. To fully exploit Diamond's superior thermal property for GaN HEMT devices, we include Aluminum Nitride (AlN) barrier in epitaxial layer structure, in addition to conventional Aluminum Gallium Nitride (AlGaN) barrier layer. The current collapse revealed very stable up to Vds = 90 V. The trapping behaviors were measured Emission Microscope (EMMI). The traps are located in interface between Silicon Nitride (SiN) passivation layer and GaN cap layer.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1982-1984
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• 1996

In this paper, we have evaluated the physical characteristicsof the Pt/Cr bilayer, fabricated the micro hot plate by using the Pt/Cr bilayer and E-beam evaporated oxide as a passivation layer, and simulated the thermal distribution by using the commercial software FIDAP. From the researches the sheet resistance of Pt/Cr bilayer didn't be affected by the Cr layer thickness. This results was considered due to the Cr-oxide resided at the interface between Pt and Cr layer. After manufacturing the hot plate, we measured its temperature by type k thermo-couple and I.R. thermo-vision system. In those experiments, the emission coefficient( ${\varepsilon}$ ) of the E-beam evaporated oxide was 0.5 and the temperature of centural region was reached about $305\;^{\circ}C$ at 1.3 watts. The temperature simulation obtained by FIDAP commercial package stewed that the temperature of centural region was about $311\;^{\circ}C$ after 5 sec.

• 한국태양에너지학회:학술대회논문집
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• 2011.04a
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• pp.116-120
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• 2011

In this paper, we studied the optimization of the screen pringting method for crystalline silicon solar cell fabrication. The 156 * 156 mm2 p-type silicon wafers with $200{\mu}m$ thickness and $0.5-3{\Omega}cm$ resistivity were used after texturing, doping, and passivation. Screen printing method is a common way to make the c-Si solar cell with low-cost and high-efficiency. We studied the optimized condition for screen printing with crystalline silicon solar cell as changing the printing direction (finger line or bus bar), finger width, and mesh angle. As a result, the screen printing with finger line direction showed higher finger height and better conversion efficiency, compared with one with bus bar direction. The experiments with various finger widths and mesh angles were also carried out. The characteristics of solar cells was obtained by measuring light current-voltage, optical microscope and electroluminescence.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.112-112
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• 2008

최근 Ruthenium (Ru) 은 높은 화학적 안정성, 누설전류에 대한 높은 저항성, 저유전체와의 높은 안정성 등과 같은 특성으로 인해 금속층-유전막-금속층 캐패시터의 하부전극으로 각광받고 있다. 또한 Cu와의 우수한 Adhesion 특성으로 인해 Cu 배선에서의 Cu 확산 방지막으로도 주목받고 있다. 그러나 이렇게 형성된 Ru 하부전극의 각 캐패시터간의 분리와 평탄화를 위해서는 CMP 공정이 도입이 필요하다. 이러한 CMP 공정에 공급되는 Slurry 에는 부식액, pH 적정제, 연마입자 등이 첨가되는데 이때 연마입자가 응집하여 Slurry의 분산 안전성 저하에 영향을 줄수 있다. 이로 인해 응집된 Slurry는 Scratch와 Delamination 과 같은 표면 결함을 유발할 수 있으며, Slurry의 저장 안정성을 저하시켜 Slurry의 물리적 화학적 특성을 변화시킬 수 있다. 그리하여 본 연구에서는 Ru CMP Slurry에서의 Surfactant와 같은 분산 안정제에 따른 Surface tension, Zeta potential, Particle size, Sedimentation의 분석을 통해 Slurry 안정성에 대한 영향을 살펴보았다. 그 결과 pH9 조건의 31ppm Dispersant 농도에서 50%이상의 Sedimentation 상승효과를 얻을 수 있었다. 또한 선택된 Surfactant가 첨가된 Ru CMP Slurry를 제조하여 Ru wafer의 Static etch rate, Passivation film thickness 와 Wettability를 비교해 보았다. 그리고 CMP 공정을 실시하여 Ru의 Removal rate와 TEOS에대한 Selectivity를 측정해 보았다.