• International Journal of Industrial Entomology and Biomaterials
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• v.5 no.2
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• pp.141-151
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• 2002

The success of sericulture industry in India is mainly attributed to the well-planned annual sericultural activity and the systematic implementation of pest preventive and control measures. The insect spectrum of silkworm and its food plants is complex and plays a major role in limiting the production of silk. Insects cause extensive damage to plant whereas predators and parasites either kill the silkworm larvae or force them to spin flimsy cocoons. Unilateral control measure against this pest is mainly based on the use of synthetic organic insecticides. Though these approaches initially paid rich dividends, the undesirable consequences soon surfaced. Insecticide induced resurgence of gall midges, leafhopper, leaf roller, secondary pest out breaks and development of pest biotypes has led to realization of Integrated Pest Management in sericulture. Various components of IPM, viz. Host plant resistance, cultural practices, biological control, chemical control and integrating them at various technological levels have been studied. Sources of host plant resistance have been identified for some of the major insect pests. High yielding mulberry variety has been propagated and their resistances towards major pests have been recorded. Cultural practices like pruning, pollarding, judicious use of nitrogen, optimum spacing and weed management have preyed to be the powerful tools in containing pests. Natural control over the pest population build- up exerted by the wide range of parasitoids, predators and pathogens has been well documented with identification of natural enemies and studies on their potential. Augmentation, through inoculation or inundative releases of parasitic arthropods, is the most direct way of increasing the numbers of these beneficials in sericulture.

• 한국균학회소식:학술대회논문집
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• 2015.05a
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• pp.54-54
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• 2015

Crops lack genetic resistance to most necrotrophic soil-borne pathogens and parasitic nematodes that are ubiquitous in agroecosystems worldwide. To overcome this disadvantage, plants recruit and nurture specific group of antagonistic microorganisms from the soil microbiome to defend their roots against pathogens and other pests. The best example of this microbe-based defense of roots is observed in disease-suppressive soils in which the suppressiveness is induced by continuously growing crops that are susceptible to a pathogen. Suppressive soils occur globally yet the microbial basis of most is still poorly described. Fusarium wilt, caused by Fusarium oxysporum f. sp. fragariae is a major disease of strawberry and is naturally suppressed in Korean fields that have undergone continuous strawberry monoculture. Here we show that members of the genus Streptomyces are the specific bacterial components of the microbiome responsible for the suppressiveness that controls Fusarium wilt of strawberry. Furthermore, genome sequencing revealed that Streptomyces griseus, which produces a novel thiopetide antibiotic, is the principal species involved in the suppressiveness. Finally, chemical-genetic studies demonstrated that S. griseus antagonizes F. oxysporum by interfering with fungal cell wall synthesis. An attack by F. oxysporum initiates a defensive "cry for help" by strawberry root and the mustering of microbial defenses led by Streptomyces. These results provide a model for future studies to elucidate the basis of microbially-based defense systems and soil suppressiveness from the field to the molecular level.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.12
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• pp.75-84
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• 2001

Due to the high density of integration in current integrated circuit layouts, circuit elements must be designed to minimize the effect of parasitic elements and thereby minimize the factors which can degrade circuit performance. Thus, before making a chip, circuit designers should check whether the extracted netlist is correct, and verify from a simulation whether the circuit performance satisfies the design specifications. In this paper, we propose a new block disassembly technique which can extract the geometric parameters of stacked MOSFETs and the distributed RCs of layout blocks. After applying this to the layout of a folded-cascode CMOS operational amplifier, we verified the connectivity and the effect of the components by simulating the extracted netlist with HSPICE.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.7
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• pp.1079-1083
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• 2002

We made ESD tester to measure ESD threshold voltage of semiconductor devices. The HBM ESD test is the most popular method to measure the ESD threshold voltage of MMSIC. We use flyback method which is one of the DC-DC converter to get high ESD voltage. With flvback method, we can isolate the 1ow voltage part from the high voltage part of HBM ESD tester. We use an air gap of the relay which is used for switch to satisfy the rise time of ESD standard(MIL-STD). As a result, with the flyback method and the air gap of relay, we can make ESD tester whose parasitic components are minimized.

• Journal of Power Electronics
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• v.18 no.2
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• pp.375-382
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• 2018

A novel active controlled primary current cutting-off zero-voltage and zero-current switching (ZVZCS) PWM three-level dc-dc converter (TLC) is proposed in this paper. The proposed converter has some attractive advantages. The OFF voltage on the primary switches is only Vin/2 due to the series connected structure. The leading-leg switches can obtain zero-voltage switching (ZVS), and the lagging-leg switches can achieve zero-current switching (ZCS) in a wide load range. Two MOSFETs, referred to as cutting-off MOSFETs, with an ultra-low on-state resistance are used as active controlled primary current cutting-off components, and the added conduction loss can be neglected. The added MOSFETs are switched ON and OFF with ZCS that is irrelevant to the load current. Thus, the auxiliary switching loss can be significantly minimized. In addition, these MOSFETs are not series connected in the circuit loop of the dc input bus bar and the primary switches, which results in a low parasitic inductance. The operation principle and some relevant analyses are provided, and a 6-kW laboratory prototype is built to verify the proposed converter.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.1
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• pp.65-71
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• 2015

This paper presents the efficiency analysis of a critical current mode interleaved PFC rectifier, in which each of three different semiconductor switches is employed as the active switch. The Si FET, SiC FET, and GaN FET are consecutively used with the prototype PFC rectifier, and the efficiency of the PFC rectifier with each different semiconductor switch is analyzed. An equivalent circuit model of the PFC rectifier, which incorporates all the internal losses of the PFC rectifier, is developed. The rms values of the current waveforms main circuit components are calculated. By adapting the rms current waveforms to the equivalent model, all the losses are broken down and individually analyzed to assess the conduction loss, switching loss, and magnetic loss in the PFC rectifier. This study revealed that the GaN FET offers the highest overall efficiency with the least loss among the three switching devices. The GaN FET yields 96% efficiency at 90 V input and 97.6% efficiency at 240 V, under full load condition. This paper also confirmed that the efficiency of the three switching devices largely depends on the turn-on resistance and parasitic capacitance of the respective switching devices.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.12
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• pp.21-26
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• 2004

In this paper, a direct method is developed to extact RF equivalent circuit of a packaged BJT without optimization. First, parasitic components of plastic package are removed from measured S-parameters using open and short package patterns. Using package do-embedded S-parameters, a direct and simple method is proposed to extract bonding wire inductance and chip pad capacitance between package lead and chip pad. The small-signal model parameters of internal BJT are next determined by Z and Y-parameter formula derived from RF equivalent circuit. The modeled S-parameters of packaged BJT agree well with measured ones, verifying the accuracy of this new extraction method.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.2
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• pp.114-121
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• 1996

Thin film Ba$^{0.7}Sr^{0.3}TiO^{3}$ (BST) capacitors were fabricated on SiO$_{2}$/Si substrates by RF magnetron sputtering method and characterized at microwave frequencies ranging from 40 MHz to 1GHz to examine the dielectric dispersion of the capacitors. The BST thin films were electrode material of BST thin films capacitor which is known as one of the best electrode materials for BST films. 50$\AA$-thick titanium (Ti) layers were introduced to increase adhesion between bottom Pt and SiO$_{2}$. The leakage current density of the capacitors was about 1.7${\times}10^{7}A/cm^{2}$ at 1.5V and the dielectric constant was about 140 at 1MHz. Microwave measurement patterns having a coplanar waveguide type were fabricated and their S parameters were measured using network analyzer. After de-embedding parasitic components in microwave measurement patterns nearly frequency-invariant dielectric constant of about 120 was extracted in the measurement range of 40 MHz to 1 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.11
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• pp.1137-1140
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• 2011

In this paper, the optimal condition for efficient active frequency multipliers is analyzed. This analysis is based on the effects from transistor nonlinear coefficients, harmonic impedances, and output parasitic components. From the analysis, normalized harmonic power is estimated with the clipping condition of a commercial transistor, and the condition for high conversion efficiency is suggested. From the analysis, a class-F frequency tripler was implemented for the output at 2.475 GHz, showing the maximum efficiency of 22.9 % and the maximum conversion gain of 9.5 dB.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.11
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• pp.17-22
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• 2000

A novel and robust direct parameter extraction method for hybrid-p equivalent circuit model of HBT is proposed. A new expression that can accurately resolve the base internal resistance from the measured S-parameters is derived, and it is not sensitive to the values of parasitic access inductance values. Based on the expression, six analytical expressions for the other parameters is developed and these expressions for hybrid-p equivalent circuit modeling ensure robust, fast, and reliable parameter extraction.